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The DC2837A board provides multiple empty mostly-0805 

component footprints for users to configure the LTC2063/

LTC2066 as desired. Common configurations and func-

tions are illustrated below. 

In the following schematics, components not mentioned 

should be left unstuffed, and jumpers not mentioned 

are not relevant.

SINGLE SUPPLY VS SPLIT RAILS

By default, the board is set up is for split supplies (V

+

, V

).

To switch to a single supply, V

+

 and GND:

1.  Remove any negative supplies from the V

 turret. This 

is important to prevent shorting the power supply out.

2.  Disconnect and change offset voltage of input signal 

source(s), then reconnect.

3.  Move jumper 

JP4

 to connect V

 and GND. All con-

nections formerly tied to V

 are now at GND.

The supplies are reverse-protected by Schottky diodes 

and bypassed with 10µF. Additional 1210 capacitors may 

be added in parallel as needed.

INPUT FILTER

As shown in Figure 3, the 10k R4 and C11 create an 

input lowpass filter at +IN. C11’s value is 33nF for a 

480Hz cutoff for LTC2063, 6.8nF for a 2.4kHz cutoff for 

LTC2066. These pass bands should be sufficient for most 

input signals.
If an input filter at –IN is desired, the resistors at R1 

and R2 may be swapped (R1 = 10k, R2 = 0Ω) and the 

capacitor C1 populated with either 33nF (for LTC2063) 

or 6.8nF (LTC2066). Jumper 

JP2

 must be installed for 

C1 to be connected.
In general, to minimize the effect of chopper clock 

feedthrough, signal bandwidths should be limited to at 

least a decade below the internal chopping frequency, 

which is 5kHz for LTC2063 and 25kHz for LTC2066.

DEFAULT: UNITY GAIN WITH INPUT FILTER

The default configuration of the board is for unity gain 

with split supplies, as shown in Figure 3. R4 is 10k for 

input protection, and R7 is 49.9Ω for 50Ω instrument 

termination. R5 = 0Ω sets gain at unity. 

JP6

 ties 

SHDN

 

to V

+

 to enable the op amp.

Figure 3. Unity Gain with +IN Lowpass Filter

OUT

1

3

JP6

C10

0.1µF

+IN

R3

R4

10k

R5

R6

R7

49.9Ω

R8

1k

V

+

2

V

ENABLED

DC2837A-B F03

S

C11

33nF/

6.8nF

V

+

V

INVERTING GAIN

 

A

V

=

– R

FB

R

G

To set the board up for inverting gain with split supplies 

(see Figure 4):
1. Populate R5 with the desired R

FB

2. Populate R2 with the desired R

G

3.  Tie +IN turret to GND (or populate Z4 with 0Ω)
4.  Connect the input signal to the –IN turret

Figure 4. Inverting Gain

OUT

1

3

–IN

+IN

J1

C10

0.1µF

R5

R

FB

R2

R

G

R1

R3

R4*

R

G

||R

FB

R8

1k

R6

R7

49.9Ω

V

+

2

V

ENABLED

*OPTIONAL

V

+

V

DC2837A-B F04

S

4

DEMO MANUAL 

DC2837A-A/DC2837A-B

Rev. 0

OPERATING PRINCIPLES

Summary of Contents for DC2837A-A

Page 1: ...wcasing the micropower zero drift op amp LTC 2063 A option or LTC2066 B option with shut down in an SC70 6 pin package The board is laid out for mostcommonopampapplicationsandleftmostlyunstuffed to maximize flexibility for a wide range of applications The DC2837A includes the SC70 package op amp jump ers unity gain configuration resistors input lowpass fil ters reverse supply protection and supply...

Page 2: ... to a GND turret Set the scaling to 100mV 2ms per division 7 Power up the system A 100Hz 0 5VP P sine wave centered at 0V should appear on the oscilloscope 8 Increase the signal amplitude and observe the signal for clipping as signals reach the supply rails Slew and settling behavior can be evaluated by switching the signal generator to square wave 9 To evaluate shutdown performance move the jumpe...

Page 3: ...4 V V V V V 2 V V V GND SHDN ENABLE SINGLE OR SPLIT SUPPLY DC BIAS DC BIAS FEEDBACK INPUT FILTER EN DIS 1 1 1 1 3 3 3 3 2 2 2 2 SPLIT SINGLE V V DC2837A B F01 S 3 DEMO MANUAL DC2837A A DC2837A B Rev 0 Figure 1 Simplified Generic Schematic QUICK START PROCEDURE Figure 2 Proper Measurement Equipment Setup POWER SUPPLY 2 50V COM SigGen 100 0Hz OSCILLOSCOPE DC2837A B F02 ...

Page 4: ... at IN is desired the resistors at R1 and R2 may be swapped R1 10k R2 0Ω and the capacitor C1 populated with either 33nF for LTC2063 or 6 8nF LTC2066 Jumper JP2 must be installed for C1 to be connected In general to minimize the effect of chopper clock feedthrough signal bandwidths should be limited to at least a decade below the internal chopping frequency which is 5kHz for LTC2063 and 25kHz for ...

Page 5: ...rt ing gain of RFB RG The DC bias added to IN is set by divider Z1 and R1 and the DC bias added to IN is set by divider R9 and R3 Figure 5 Non Inverting Gain R4 may be optionally populated with a resistor equivalent to RG RFB for increased precision over temperature R4 will cancel out IB and potential parasitic thermocouples at the inputs OUT 1 3 IN IN J1 C10 0 1µF R1 0Ω R3 0Ω R2 RG R4 RG RFB R6 0...

Page 6: ...s connected at the inputs can poten tially lead to clock feedthrough appearing in the output especially if the gain setting of the amplifier is not high enough that GBW roll off will naturally attenuate signals at the clock frequency Placing a capacitor in parallel with a large RFB can help filter out this undesired clock signal On this board if RFB is R5 a filter capacitor can be stuffed in Z2 if...

Page 7: ... Filter Component Values BUTTERWORTH BESSEL R1 681k 806k R2 169k 88 7k Z1 681k 806k C1 10nF 10nF C2 2 2nF 2 2nF Figure 8 Building A Second Order Active Lowpass Filter with DC2837A 1 Stuff Z6 with 0Ω to tie IN to GND 2 Remove C11 and R5 3 Stuff C1 leave JP2 connected OUT 1 3 IN JP6 C10 0 1µF R2 R1 R8 1k R6 0Ω R7 49 9Ω C1 Z1 JP5 JP2 JP1 R5 C R5 Z6 0Ω V 2 V ENABLED DC2837A B F08 S 4 Replace R1 and R2...

Page 8: ... not disclose or transfer any portion of the Evaluation Board to any other party for any reason Upon discontinuation of use of the Evaluation Board or termination of this Agreement Customer agrees to promptly return the Evaluation Board to ADI ADDITIONAL RESTRICTIONS Customer may not disassemble decompile or reverse engineer chips on the Evaluation Board Customer shall inform ADI of any occurred d...

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