Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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Register Descriptions
11-44 ADSP-BF537 Blackfin Processor Hardware Reference
Although peripheral bus writes are 16 bits, a write access to
TWI_XMT_DATA8
adds only one transmit data byte to the FIFO buffer. With
each access, the transmit status (
XMTSTAT
) field in the
TWI_FIFO_STAT
regis-
ter is updated. If an access is performed while the FIFO buffer is full, the
write is ignored and the existing FIFO buffer data and its status remains
unchanged.
TWI_XMT_DATA16 Register
The TWI FIFO transmit data double byte register (
TWI_XMT_DATA16
)
holds a 16-bit data value written into the FIFO buffer. To reduce inter-
rupt output rates and peripheral bus access times, a double byte transfer
data access can be performed. Two data bytes can be written, effectively
filling the transmit FIFO buffer with a single access. The data is written in
little endian byte order as shown in
Figure 11-24 where byte 0 is the first
byte to be transferred and byte 1 is the second byte to be transferred. With
each access, the transmit status (
XMTSTAT
) field in the
TWI_FIFO_STAT
Figure 11-23. TWI FIFO Transmit Data Single Byte Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TWI FIFO Transmit Data Single Byte Register (TWI_XMT_DATA8)
All bits are WO.
XMTDATA8[7:0] (Transmit
FIFO 8-Bit Data)
Reset = 0x0000 0xFFC0 1480