Analog Devices Blackfin ADSP-BF537, Hardware Reference Manual

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ADSP-BF537 Blackfin Processor Hardware Reference 11-45
Two Wire Interface Controller
register is updated. If an access is performed while the FIFO buffer is not
empty, the write is ignored and the existing FIFO buffer data and its sta-
tus remains unchanged.
TWI_RCV_DATA8 Register
The TWI FIFO receive data single byte register (
TWI_RCV_DATA8
) holds an
8-bit data value read from the FIFO buffer. Receive data is read from the
corresponding receive buffer in a first-in first-out order. Although periph-
eral bus reads are 16 bits, a read access to
TWI_RCV_DATA8
will access only
one transmit data byte from the FIFO buffer. With each access, the
Figure 11-24. Little Endian Byte Order
Figure 11-25. TWI FIFO Transmit Data Double Byte Register
B1 B0
DATA IN REGISTER
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TWI FIFO Transmit Data Double Byte Register (TWI_XMT_DATA16)
All bits are WO. This register always reads as 0x0000.
XMTDATA16[15:0] (Transmit
FIFO 16-Bit Data)
Reset = 0x0000 0xFFC0 1484