System Architecture
2-4
Blackfin A-V EZ-Extender Manual
summarizes the signals coming and going on the expansion
interface connectors.
Table 2-1. Signals of Expansion Interface Connectors
Net/Bus Name
(Direction)
Blackfin A-V EZ-Extender Function
Relevant
Configuration
Jumpers
PPI0_D[0:15]
(Bi)
Connects the processor’s
PPI0
data pins to the
VID_IN_D[0:15]
or
VID_OUT_D[0:15]
buses, depend-
ing on the jumper settings. This allows
PPI0
to interface
with all video interfaces on the board. The bus can be
bidirectional, where the direction is fixed with a jumper
or controlled by a flag pin.
JP5.3/4
,
JP9.2/4/6
PPI0_CLK
(Output)
The clock related to the data on
PPI0
. This can come
from an on-board oscillator, one of the video interfaces,
or a socket that allows a user-supplied oscillator.
JP4.1/2
,
JP4.3/4
,
JP4.5/6
,
JP4.7/8
PPI0_SYNC1
(Bi)
The frame sync signal going to the processor’s
PPI0_SYNC1
pin. The signal behaves as
HSYNC
or
HREF
for the video interfaces. The signal also can be used to
drive the FPDI’s
HS
signal. The signal can be bidirec-
tional, where the direction is fixed with a jumper or con-
trolled by a flag pin.
JP6.1/3/5
,
JP8.1/3/5
,
JP8.7/8
PPI0_SYNC2
(Bi)
The frame sync signal going to the processor’s
PPI0_SYNC2
pin. The signal behaves as
VSYNC
or
VREF
for the video interfaces. In addition, the signal can drive
the FPDI’s
VS
signal. The signal can be bidirectional,
where the direction is fixed with a jumper or controlled
by a flag pin.
JP6.2/4/6
,
JP8.2/4/6
,
JP8.7/8
PPI1_D[0:15]
(Bi)
Connects the processor’s
PPI1
data pins to the
VID_OUT_D[0:15]
bus. The
VID_OUT_D[0:15]
bus
interfaces with the output video interfaces (FPDI and
video encoder). The bus can be bidirectional but intended
to be an input. Changing the direction is necessary only
for test purposes and allows
PPI0
to loop-back to
PPI1
.
Note:
D2
,
D3
, and
D10
of the bus have other functions
(follows).
JP5.3/4
,
JP5.5/6
,
JP3.9/10
,
JP3.3/5/7
JP3.4/6/8
