UG-707
ADV8005 Hardware Reference Manual
Figure 111: Simplified View of
Encoder Block
The video being routed to the SD and ED/HD encoders can be selected through the 0x0004[7:4] register (ED/HD encoder) and 0x0004[3:0]
(SD encoder). Refer Section
Once the desired video has been routed to the encoder, the mode of the incoming video data needs to be set using
func_mode[2:0]
, Encoder Map,
Address 0xE401[6:4]
This signal is used to select the input mode to the encoder.
Function
func_mode[2:0]
Description
000 (default)
SD Input Only
001
ED/HD-SDR input only
010
Reserved
011
Simultaneous SD and ED/HD-SDR
100
Reserved
101
Reserved
110
Reserved
111
Reserved
Once the input configuration to the encoder section is configured, the input standard to the SD and/or HD encoder must be selected.
lists the possible input standards supported by the
encoder core. Note that if using the
de-interlacer and/or scaler, the input
standard of the encoder must be set to that of the output of the VSP section. If bypassing the VSP section, the user should set this to the standard
of the external input video.
If configuring the HD encoder, the input standard must be set using
S
D
E
NCODER
A
D
V
8
0
05
E
N
C
O
D
E
R
P
R
O
C
E
S
S
O
R
H
D
E
N
C
O
D
E
R
M
U
X
1
4
-
B
I
T
D
A
C
1
D
A
C
1
1
6
/
2
0
/
2
4
-
BI
T
Y
C
b
C
r
4
:4:4
V
I
D
E
O
F
R
O
M
I
N
T
E
R
N
A
L
A
D
V
8
0
0
2
D
A
T
A
P
A
T
H
V
I
D
E
O
F
R
O
M
I
N
T
E
R
N
A
L
A
D
V
8
0
0
2
D
A
T
A
P
A
T
H
2
4
/
3
0
/
3
6
-
BI
T
Y
C
b
C
r
4
:
4
:
4
1
4
-
B
I
T
D
A
C
2
D
A
C
2
1
4
-
B
I
T
D
A
C
3
D
A
C
3
1
4
-
B
I
T
D
A
C
4
D
A
C
4
1
4
-
B
I
T
D
A
C
5
D
A
C
5
1
4
-
B
I
T
D
A
C
6
D
A
C
6
4:4:4 to 4:2:2
Conversion
Rev. A | Page 244 of 317
