Analog Devices ADV8003, Hardware Manual

Page: 146 / 440

ADV8003 Hardware Manual
Rev. B, August 2013 146
Function
pvsp_enable_ffs Description
0  Disable FFS/FRC
1 Enable FFS/FRC
3.2.1.1. Autoconfiguration
Each block inside VIM and VOM can be automatically configured to reduce the configuration complexity. Two registers,
pvsp_autocfg_input_vid[7:0] and pvsp_autocfg_output_vid[7:0] should be set to make the autoconfiguration work.
The 59.94/23.97 Hz timings have the same VID as the corresponding 60/24Hz timing in Figure 24 .
pvsp_autocfg_input_vid[7:0]
, Primary VSP Map,
Address 0xE881[7:0]
This register is used to set the input timing VIC. If this register is 0, PVSP will use values in registers of pvsp_vin_h, pvsp_vin_v,
pvsp_is_i_to_p and pvsp_vin_fr to set input video.
Function
pvsp_autocfg_input_vi
d[7:0]
Description
0x06  Default: 480i@60
0xXX Input timing VID
Table 22: PVSP Supported Input Video Timing and VID
Video Timing VID
CEA
640x480p60 1
720x480p60 2 or 3 or 14 or 15 or 35 or 36
720x240p60 8 or 9 or 12 or 13
1280x720p60 4
1920x1080i60 5
720x480i60 6 or 7 or 10 or 11
1920x1080p 16
720x576p50 17 or 18 or 29 or 30 or 37 or 38
1280x720p50 19
1920x1080i50 20
720x576i50 21 or 22 or 25 or 26
720x288p50 23 or 24 or 27 or 28
1920x1080p50 31
1920x1080p24 32
1920x1080p25 33
1920x1080p30 34
1080i50-even 39
1080i100 40
720p100 41
576p100 42 or 43
576i100 44 or 45
1080i120 46
720p120 47
480p120 48 or 49
480i120 50 or 51
576p200 52 or 53
576i200 54 or 55