17000055 - Flash Security Features Are Not Fully Operational:
DESCRIPTION:
All the security features and key management processes may be exercised. However, flash memory contents are not fully protected by
the security measures even if the part is locked. Security measures are planned to be fully functional in production silicon.
WORKAROUND:
None.
APPLIES TO REVISION(S):
0.0
17000057 - PLL Malfunctions at Higher Frequencies:
DESCRIPTION:
The Clock Generation Unit (CGU) derives all the processor clocks from the phase-locked loop (PLL) voltage-controlled oscillator (VCO)
output, called PLLCLK. When PLLCLK is configured to operate at frequencies above 600 MHz, it may malfunction.
WORKAROUND:
Configure the processor PLL such that the PLLCLK frequency does not exceed 600 MHz.
For example, consider an application that requires a CCLK:SYSCLK ratio of 240:96, with a SYS_CLKIN of 24 MHz. Set
CGU_CTL.MSEL
= 20
(480 MHz), and adjust the divisors by setting
CGU_DIV.CSEL
= 2 and
CGU_DIV.SYSSEL
= 5. This ensures that the PLL clock frequency
does not exceed 600 MHz and the core clock/system clock frequency requirements are met.
APPLIES TO REVISION(S):
0.0
17000059 - Security Keys for Devices Connected in a JTAG Chain Require Leading Zeroes:
DESCRIPTION:
When multiple ADSP-CM41x controllers are placed in a JTAG scan chain, the first part in the chain uses all 128 user debug security bits. For
all other parts, zeroes are appended with respect to the position of the part in the scan chain. This issue occurs when security keys are
provided through the TAPC security scan path.
For example, if three ADSP-CM41x parts are connected in series in the JTAG chain:
• The first part in the chain uses all 128 security bits ([127:0]).
• The second part in the chain uses 127 security bits ([127:1]). Bit 0 is set to 0.
• The third part in the chain uses 126 security bits ([127:2]). Bits 0 and 1 are both set to 0.
The example assumes that the parts are connected as individual JTAG controllers. The issue can also occur if multiple tap controllers are
enabled in the scan chain, resulting in multiple zeroes from each part, and when non-ADSP-CM41x devices are included in the scan chain.
WORKAROUND:
Use memory-mapped writes through the DAP instead of the TAPC security scan path to provide security keys.
APPLIES TO REVISION(S):
0.0
17000060 - adi_rom_MemCopy() ROM API Leaves MDMA Enabled:
DESCRIPTION:
The
adi_rom_MemCopy()
function in the ROM does not disable the MDMA channels upon completion. This may result in MDMA errors
when the application attempts to reprogram the MDMA channels. This issue occurs with both ROM API and application code.
WORKAROUND:
Application code must manually disable the MDMA source and destination channels after calling the
adi_rom_MemCopy()
routine by
setting
DMA12_CFG.EN
= 0 and
DMA13_CFG.EN
= 0.
APPLIES TO REVISION(S):
0.0
ADSP-CM411F/412F/413F/416F/417F/418F/419F
NR004483C | Page 7 of 12 | July 2017
Silicon Anomaly List
