ADSP-2126x SHARC Processor Hardware Reference
A-9
Registers Reference
Mode Mask Register (MMASK)
This is a non memory-mapped, universal, system register (
Ureg
and
Sreg
).
Each bit in the
MMASK
register corresponds to a bit in the
MODE1
register.
Bits that are set in the
MMASK
register are used to clear bits in the
MODE1
reg-
ister when the processor’s status stack is pushed. This effectively disables
different modes upon servicing an interrupt, or when executing a
PUSH
STS
instruction.
provides bit information for the
MMASK
register.
4
CADIS
Cache Disable.
This bit disables the instruction cache (if set, = 1)
or enables the cache (if cleared, = 0). If this bit is set, then the
caching of instructions from internal memory and external mem-
ory both are disabled (see bit 6).
5
TIMEN
Timer Enable.
Enables the core timer (starts, if set, = 1) or disables
the core timer (stops, if cleared, = 0).
6
EXTCADIS
External Cache Only Disable.
Disables the caching of the instruc-
tions coming from external memory (if set, =1) or enables caching
of the instructions coming from external memory (if cleared, = 0
and CADIS bit 4 = 0). This bit can only be used with the
ADSP-214xx products.
18–7
Reserved
19
CAFRZ
Cache Freeze.
Freezes the instruction cache (retain contents if set,
= 1) or thaws the cache (allow new input if cleared, = 0).
20
IIRAE
Illegal I/O Processor Register Access Enable.
Enables (if set, = 1)
or disables (if cleared, = 0) detection of I/O processor register
accesses. If IIRAE is set, the processor flags an illegal access by set-
ting the IIRA bit in the STKYx register.
21
U64MAE
Unaligned 64-Bit Memory Access Enable.
Enables (if set, = 1) or
disables (if cleared, = 0) detection of unaligned long word accesses.
If U64MAE is set, the processor flags an unaligned long word
access by setting the U64MA bit in the STKYx register.
31–22
Reserved
Table A-3. Mode Control 2 Register (MODE2) Bit Descriptions (Cont’d)
Bit
Name
Description
Summary of Contents for ADSP-21261 SHARC
Page 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Page 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Page 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Page 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Page 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Page 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Page 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Page 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Page 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Page 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Page 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Page 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...