EPROM addressing differs, depending on the silicon revision of the ADSP-21065L on your EZ-
KIT Lite board. For revision 0.1 silicon, EPROM addressing begins at address 0x020000. For
revision 0.2 and greater, addressing begins at address 0x000000 (i.e. you can use all memory
space, see Figure 5-4).
5.6.1 Designers Note
When JP6 is removed or connected to GND, the ADSP-21065L is initialized to boot from the
EPROM. On this board, the ACK line is used to control wait states.
Figure 5-4 EPROM Address (256K x 8 example)
5.7 UART
The UART used is a 5V part; therefore, a 74LVTH245 is used to translate the data coming from
the UART to the required 3.3V logic needed by the processor.
5.7.1 Designers Note
To access the UART correctly, the relationship between the timing of the data, chip select,
and the read/write lines needed to be changed. Most of these changes were implemented
through a CPLD. An additional 10ns delay was needed on the control lines. Since this delay
was not possible through the CPLD, a digital delay was added to the circuit.
It is important to note that the UART and the CPLD only decode a subset of the available
address lines. Because of this partial decoding, the UART is aliased throughout the MS1
address space.
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