Preliminary Technical Data
UG-1828
Rev. PrC | Page 287 of 338
ADI_ADRV9001_LDO_POWER_SAVING_MODE_2, ADI_ADRV9001_LDO_POWER_SAVING_MODE_1,
ADI_ADRV9001_LDO_POWER_SAVING_MODE_1, ADI_ADRV9001_LDO_POWER_SAVING_MODE_1 }
In this case it is still assumed that 2T/2R channels are still being used. If it’s the case that the user application only uses Tx1 and Rx1 then
the LDOs for those channels can be set to a bypass or power down mode along with hardware modifications. There is a relationship
between the hardware power layout and the LDO mode so attention is needed to correctly set the part to reflect the physical
implementation. Attention is needed when bypassing LDOs to make sure that internal circuits are not supplied with incorrect voltage
levels.
EXAMPLE:
TDD operation using Tx1, Rx1 and external LOs
The hardware power setup will look like Figure 267 where the pins for the Tx2 and Rx2 1v and 1.3v LO domains are tied to ground. The
LDOs powering these RF blocks, VANA2_1p0 and VANA2_1p3, are also tied to ground because they are not needed.
VDDA_1P8
5% tol.
VDD_1.0V
5% tol.
VDIG_1P0 (L7,L8)
VDD_1P8
5% tol.
VDDA_1P3
2.5% tol.
VDIGIO_1P8 (M7)
VDIG_0P9 (M8)
VCONV_1P8 (G7)
VAGPIO_1P8 (G8)
VANA1_1P8 (H13) +
External Tx1 pull-ups
VANA2_1P8 (H2) +
External Tx2 pull-ups
VRFSYN1_1P3 (E11)
VRFSYN2_1P3 (E4)
VAUXSYN_1P3 (E10)
VCLKSYN_1P3 (E5)
VRFVC01_1P3 (A10)
VRFVC02_1P3 (A5)
VCLKVCO_1P3 (G5)
VAUXVCO_1P3 (G10)
VANA1_1P3 (C8)
VANA2_1P3 (C7)
VRFVCO1_1P0 (B9)
VRFLO1_1P0 (A9)
VRFVCO2_1P0 (B6)
VRFLO2_1P0 (A6)
VCONV_1P3 (H8)
VRX1LO_1P3 (E13)
VRX2LO_1P3 (E2)
VTX1LO_1P3 (G12)
VTX2LO_1P3 (G3)
VCLKVCO_1P0 (H5)
VAUXVCO_1P0 (H10)
VCONV_1P0 (H7)
VRX1LO_1P0 (E14)
VRX2LO_1P0 (E1)
VTX1LO_1P0 (H12)
VTX2LO_1P0 (H3)
VANA2_1P0 (C6)
VANA1_1P0 (C9)
4.7µF
4.7µF
Not connected
4.7µF
Not connected
Standard operating
Configuration 0
All internal LDOs used
Internal LO generation used.
VDDA_1P3
2.5% tol.
VRFSYN1_1P3 (E11)
VRFSYN2_1P3 (E4)
VAUXSYN_1P3 (E10)
VCLKSYN_1P3 (E5)
VRFVC01_1P3 (A10)
VRFVC02_1P3 (A5)
VCLKVCO_1P3 (G5)
VAUXVCO_1P3 (G10)
VANA1_1P3 (C8)
VANA2_1P3 (C7)
VRFVCO1_1P0 (B9)
VRFLO1_1P0 (A9)
VRFVCO2_1P0 (B6)
VRFLO2_1P0 (A6)
VCONV_1P3 (H8)
VRX1LO_1P3 (E13)
VRX2LO_1P3 (E2)
VTX1LO_1P3 (G12)
VTX2LO_1P3 (G3)
VDDA_1P0
2.5% tol.
Internal PLLs not used for LOs.
LO GEN supply disconnected
and powered down internally.
Low power operation
Configuration 2 Some internal
LDOs bypassed, External LO
generation used.
VANA2_1P3 (C7)
VRX2LO_1P3 (E2)
VTX2LO_1P3 (G3)
VANA2_1P0 (C6)
VTX2LO_1P0 (H3)
Rx1/Tx1 used
Rx2/Tx2 not used
VRX2LO_1P0 (E1)
Low power operation
Configuration 2 Some internal
LDOs bypassed, External LO
generation used.
+
+
Figure 267. Standard Operating Config 0 & External LO Config & Rx1/Tx1 Power Supply Config
When the external LO config and Rx1/Tx1 config are super-positioned onto the standard operating configuration the power supplies are
connected as per Figure 268.
