UG-057
ADP1872-EVALZ/ADP1873-EVALZ User Guide
Rev. A | Page 4 of 20
Placeholders for SMB jacks are integrated into each evaluation
board to facilitate such connections. Therefore, to accurately
measure V
IN
, connect the voltmeter’s positive terminal (+) to
the node where the positive terminal of the high voltage input
capacitors (C3 to C8) and the drain of Q1/Q2 meet, and connect
the voltmeter’s negative terminal (−) to the node where the negative
terminal of the input capacitors and the source terminal of Q3
meet. These SMB terminals are optimally placed to minimize
unnecessary voltage drops that may otherwise produce inaccurate
VIN dc measurements.
Similarly, for output voltage (V
OUT
) dc measurements, a place-
holder for an SMB terminal is positioned directly across the
positive and negative terminals of the output capacitor that
is farthest from the inductor terminal and source of Q3. For
accurate low input voltage (V
DD
) dc measurements, an SMB
terminal footprint is positioned as close as possible across C1,
which is laid out near the VDD pin (Pin 5) and the PGND pin
(Pin 7) of the
ADP1872
/
ADP1873
.
POWERING UP AND POWERING DOWN
THE EVALUATION BOARD
After completing the procedure described in the Setting Up the
Evaluation Board section, power up the evaluation board as
follows:
1.
Apply power to the VDD pin.
2.
Apply power to the VIN pin.
3.
Slowly increase the V
DD
supply while monitoring the current
meter until V
DD
is equal to 5 V.
Because V
IN
is 0 V, I
DD
should jump between 120 µA (when
approaching the UVLO threshold of 2.65 V) to less than 1 mA
until V
DD
is equal to 5 V. Do not exceed 5.5 V on V
DD
. No
output (V
OUT
) regulation is expected yet because V
IN
is 0 V.
4.
Slowly increase V
IN
up to 12 V.
When V
IN
is increased, V
OUT
begins regulating to the desired
voltage setpoint (via the V
OUT
dedicated voltmeter). Continue
to increase V
IN
up to 12 V. Do not exceed 20 V on V
IN
. Output
voltage regulation should occur regardless of whether there is
a load connected at the output.
5.
After the output voltage is in regulation with the desired input
voltage, increase the electronic load to the desired value.
To power down the evaluation board,
1.
Power down V
IN
.
2.
Power down V
DD
.
ENABLING AND DISABLING
THE
ADP1872
/
ADP1873
The
ADP1872
/
ADP1873
evaluation board has a placeholder for
a switch (normally open) for the COMP/EN pin to allow you to
enable (open) and disable (closed) the
ADP1872
/
ADP1873
on
the evaluation board. When closed, the switch shorts this pin to
ground, disabling the
ADP1872
/
ADP1873
. When the switch is
subsequently opened (released), the error amplifier brings the
voltage on this pin above the enable threshold of 285 mV, thus
enabling the IC, which causes the output voltage to regulate.
EVALUATING THE PERFORMANCE
OF THE
ADP1872
/
ADP1873
Verifying the Switching Waveform
To verify the switching waveform,
1.
Ensure that the oscilloscope, probe tips, and ground loop clip
are in good working condition; that the probe tips have been
calibrated per the manufacturer’s instructions and are clear
of debris and dirt; and that the ground loops do not have any
breaks or peels.
2.
Set the operating mode of the respective oscilloscope to
DC Coupling in the oscilloscope’s Channel menu.
3.
Set the bandwidth to its maximum value (≥150 MHz).
4.
Set the vertical scale to 5 V per division and the timescale
(x-axis) to 1/(2 × f
SW
) per division, where f
SW
is the switching
frequency of the evaluation board.
5.
Securely attach the ground loop clip onto the TP_PGND
terminal of the evaluation board. Ideally, the loop should
be as close as possible to the negative terminal of the high
input voltage capacitors (C3 to C8) and to the source of
MOSFET Q1.
6.
Land or securely attach the probe tip to the drain of Q1.
7.
Observe the subsequent switching waveform and jitter.
The resultant switching waveform should be between 0 V and
the value of V
IN
(that is, 12 V), and the jitter should be less than
or equal to 100 ns.
Observing the Output Voltage Ripple
To observe the output voltage ripple,
1.
Set the operating mode of the respective oscilloscope to
AC Coupling in the oscilloscope’s Channel menu.
2.
Set the vertical scale to 100 mV per division and the timescale
to 1/(2 × f
SW
).
3.
Securely attach the ground loop clip onto the TP_PGND
terminal of the evaluation board. Ideally, the loop should
be as close as possible to the negative terminal (−) of the
farthest output capacitor from the inductor terminal, and
the probe tip should touch the positive terminal (+) of the
same output capacitor.
4.
Observe the output voltage ripple.
Evaluating the Inductor Current Waveform
To evaluate the inductor current waveform,
1.
Calibrate the current probe per the manufacturer’s
instructions.
2.
Power up the system (see the Powering Up and Powering
Down the Evaluation Board section).
3.
Solder a 3 inch wire loop (from 10 gauge to 14 gauge) between
the source of Q1 and the inductor terminal. The current probe
has a clamping mechanism and can clamp onto this wire to
measure the current traveling through the wire.
