ADAV4622
Rev. B | Page 9 of
28
TIMING SPECIFICATIONS
Table 2.
Parameter Description
Min
Max
Unit
Comments
MASTER CLOCK AND RESET
f
MCLKI
MCLKI
frequency
3.072
24.576
MHz
t
MCH
MCLKI
high
10
ns
t
MCL
MCLKI
low
10
ns
t
RESET
RESET low
200
ns
MASTER CLOCK OUTPUT
t
JIT
Period jitter
800 ps
t
CH
MCLK_OUT
high
45
55
%
t
CL
MCLK_OUT
low
45
55
%
I
2
C PORT
f
SCL
SCL clock frequency
400
kHz
t
SCLH
SCL
high
600
ns
t
SCLL
SCL
low
1.3
μs
Start Condition
t
SCS
Setup time
600
ns
Relevant for repeated start condition
t
SCH
Hold time
600
ns
After this period, the first clock is generated
t
DS
Data setup time
100
ns
t
SCR
SCL rise time
300
ns
t
SCF
SCL fall time
300
ns
t
SDR
SDA rise time
300
ns
t
SDF
SDA fall time
300
ns
Stop Condition
t
SCS
Setup
time
0
ns
SERIAL PORTS
Slave Mode
t
SBH
BCLK
high
40
ns
t
SBL
BCLK
low
40
ns
f
SBF
BCLK frequency
64 × f
S
t
SLS
LRCLK setup
10
ns
To BCLK rising edge
t
SLH
LRCLK hold
10
ns
From BCLK rising edge
t
SDS
SDIN setup
10
ns
To BCLK rising edge
t
SDH
SDIN hold
10
ns
From BCLK rising edge
t
SDD
SDO delay
50
ns
From BCLK falling edge
Master Mode
t
MLD
LRCLK delay
25
ns
From BCLK falling edge
t
MDD
SDO delay
15
ns
From BCLK falling edge
t
MDS
SDIN setup
10
ns
From BCLK rising edge
t
MDH
SDIN hold
10
ns
From BCLK rising edge
