Analog Devices ADAU1961 Manual Download Page 9

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ADAU1961

Rev. 0 | Page 9 of

DIGITAL TIMING SPECIFICATIONS

−40°C < T

< +105°C, IOVDD = 3.3 V ± 10%.

Table 6. Digital Timing

Parameter

Limit

Unit Description

MIN

MAX

MASTER CLOCK

488

MCLK period, 256 × f

mode.

244

MCLK period, 512 × f

mode.

24.7

162.7

MCLK period, 768 × f

mode.

18.5

122

MCLK period, 1024 × f

mode.

SERIAL PORT

BIL

BCLK pulse width low.

BIH

BCLK pulse width high.

LIS

LRCLK setup. Time to BCLK rising.

LIH

LRCLK hold. Time from BCLK rising.

SIS

DAC_SDATA setup. Time to BCLK rising.

SIH

DAC_SDATA hold. Time from BCLK rising.

SODM

ADC_SDATA delay. Time from BCLK falling in master mode.

SPI PORT

CCLK

MHz

CCLK

frequency.

CCPL

CCLK pulse width low.

CCPH

CCLK pulse width high.

CLS

CLATCH setup. Time to CCLK rising.

CLH

CLATCH hold. Time from CCLK rising.

CLPH

CLATCH pulse width high.

CDS

CDATA setup. Time to CCLK rising.

CDH

CDATA hold. Time from CCLK rising.

COD

COUT three-stated. Time from CLATCH rising.

C PORT

SCL

400

kHz

SCL

frequency.

SCLH

0.6

μs

SCL

high.

SCLL

1.3

μs

SCL

low.

SCS

0.6

μs

Setup time; relevant for repeated start condition.

SCH

0.6

μs

Hold time. After this period, the first clock is generated.

100

Data setup time.

SCR

300

SCL rise time.

SCF

300

SCL fall time.

SDR

300

SDA rise time.

SDF

300

SDA fall time.

BFT

0.6

μs

Bus-free time. Time between stop and start.

DIGITAL MICROPHONE

LOAD

= 1 MΩ, C

LOAD

= 14 pF.

DCF

Digital microphone clock fall time.

DCR

Digital microphone clock rise time.

DDV

Digital microphone delay time for valid data.

DDH

Digital microphone delay time for data three-stated.

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Summary of Contents for ADAU1961

Page 1: ...iers Navigation systems Rear seat entertainment systems GENERAL DESCRIPTION The ADAU1961 is a low power stereo audio codec that supports stereo 48 kHz record and playback at 35 mW from a 3 3 V analog supply The stereo audio ADCs and DACs support sample rates from 8 kHz to 96 kHz as well as a digital volume control The record path includes an integrated microphone bias circuit and six inputs The in...

Page 2: ...22 Digital Power Supply 22 Input Output Power Supply 22 Clock Generation and Management 22 Clocking and Sampling Rates 24 Core Clock 24 Sampling Rates 24 PLL 25 Record Signal Path 27 Input Signal Paths 27 Analog to Digital Converters 29 Automatic Level Control ALC 30 ALC Parameters 30 Noise Gate Function 31 Playback Signal Path 33 Output Signal Paths 33 Headphone Output 34 Pop and Click Suppressio...

Page 3: ...All gains 105 kΩ SINGLE ENDED LINE INPUT Full Scale Input Voltage 0 dB 1 0 2 83 V rms V p p Dynamic Range 20 Hz to 20 kHz 60 dB input With A Weighted Filter RMS 83 5 99 dB No Filter RMS 83 96 dB Total Harmonic Distortion Noise 1 dBFS 90 71 dB Signal to Noise Ratio With A Weighted Filter RMS 99 dB No Filter RMS 96 dB Input Mixer Gain per Step 12 dB to 6 dB range 2 89 3 3 07 dB Mute Attenuation LINP...

Page 4: ... 1 0 LDBOOST 1 0 00 87 82 dB Interchannel Gain Mismatch 0 3 0 0005 0 3 dB Offset Error 6 0 6 mV Gain Error 17 14 9 Interchannel Isolation 83 dB Common Mode Rejection Ratio 100 mV rms 1 kHz 58 dB 100 mV rms 20 kHz 52 48 44 dB MICROPHONE BIAS MBIEN 1 Bias Voltage 0 65 AVDD MBI 1 MPERF 0 2 00 2 145 2 19 V MBI 1 MPERF 1 2 04 2 13 2 21 V 0 90 AVDD MBI 0 MPERF 0 2 89 2 97 3 04 V MBI 0 MPERF 1 2 89 2 99 ...

Page 5: ...ale Output Voltage 0 dB Scales linearly with AVDD 0 92 2 60 V rms V p p Total Harmonic Distortion Noise 4 dBFS 16 Ω load PO 21 1 mW 82 dB 4 dBFS 32 Ω load PO 10 6 mW 82 dB Capless Headphone Mode 2 dBFS 16 Ω load 78 71 dB 2 dBFS 32 Ω load 75 65 dB Headphone Output Mode 0 dBFS 10 kΩ load 86 77 dB Interchannel Isolation 1 kHz 0 dBFS input signal 32 Ω load Referred to GND 73 dB Referred to CM capless ...

Page 6: ...PGA muted LDMUTE RDMUTE 0 73 dB RDBOOST 1 0 LDBOOST 1 0 00 82 dB Interchannel Gain Mismatch 0 4 0 4 dB Offset Error 6 6 mV Gain Error 21 7 Common Mode Rejection Ratio 100 mV rms 1 kHz 64 38 dB 100 mV rms 20 kHz 53 43 dB MICROPHONE BIAS MBIEN 1 Bias Voltage 0 65 AVDD MBI 1 MPERF 0 1 85 2 45 V MBI 1 MPERF 1 1 87 2 45 V 0 90 AVDD MBI 0 MPERF 0 2 65 3 40 V MBI 0 MPERF 1 2 65 3 40 V Noise in the Signal...

Page 7: ... 3 3 V 10 For total power consumption add the IOVDD current listed in Table 3 Table 3 Parameter Test Conditions Comments Min Typ Max Unit SUPPLIES Voltage DVDDOUT 1 56 V AVDD 2 97 3 3 3 65 V IOVDD 2 97 3 3 3 65 V Digital I O Current IOVDD 20 pF capacitive load on all digital pins Slave Mode fS 48 kHz 0 48 mA fS 96 kHz 0 9 mA fS 8 kHz 0 13 mA Master Mode fS 48 kHz 1 51 mA fS 96 kHz 3 mA fS 8 kHz 0 ...

Page 8: ...354 fS 61 kHz Stop Band Attenuation 48 kHz mode typ 48 kHz 69 dB 96 kHz mode typ 96 kHz 68 dB Group Delay 48 kHz mode typ 48 kHz 25 fS 521 μs 96 kHz mode typ 96 kHz 11 fS 115 μs DIGITAL INPUT OUTPUT SPECIFICATIONS 40 C TA 105 C IOVDD 3 3 V 10 Table 5 Parameter Test Conditions Comments Min Typ Max Unit INPUT SPECIFICATIONS Input Voltage High VIH 0 7 IOVDD V Input Voltage Low VIL 0 3 IOVDD V Input L...

Page 9: ...TCH setup Time to CCLK rising tCLH 10 ns CLATCH hold Time from CCLK rising tCLPH 10 ns CLATCH pulse width high tCDS 5 ns CDATA setup Time to CCLK rising tCDH 5 ns CDATA hold Time from CCLK rising tCOD 50 ns COUT three stated Time from CLATCH rising I2 C PORT fSCL 400 kHz SCL frequency tSCLH 0 6 μs SCL high tSCLL 1 3 μs SCL low tSCS 0 6 μs Setup time relevant for repeated start condition tSCH 0 6 μ...

Page 10: ... 16 BIT DATA tLIS tSIS tSIH tSIH tSIS tSIS tSIH tSIS tSIH tLIH tBIL 08915 002 Figure 2 Serial Input Port Timing BCLK LRCLK ADC_SDATA LEFT JUSTIFIED MODE LSB ADC_SDATA I2S MODE ADC_SDATA RIGHT JUSTIFIED MODE tBIH MSB MSB 1 MSB MSB 8 BIT CLOCKS 24 BIT DATA 12 BIT CLOCKS 20 BIT DATA 14 BIT CLOCKS 18 BIT DATA 16 BIT CLOCKS 16 BIT DATA tSODM tBIL tSODM tSODM 08915 003 Figure 3 Serial Output Port Timing...

Page 11: ...915 004 Figure 4 SPI Port Timing tSCH tSCLH tSCR tDS SDA tSCLL tSCF SCL tSCH tBFT tSCS 08915 005 Figure 5 I2 C Port Timing CLK DATA1 DATA2 DATA1 DATA1 DATA2 DATA2 08915 006 tDCF tDDH tDDH tDDV tDDV tDCR Figure 6 Digital Microphone Timing Downloaded from Elcodis com electronic components distributor ...

Page 12: ...pre sents thermal resistance junction to case All characteristics are for a 4 layer board Table 8 Thermal Resistance Package Type θJA θJC Unit 32 Lead LFCSP 50 1 17 C W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the opera...

Page 13: ...nd read write bit that are sent at the beginning of the SPI transaction 4 JACKDET MICIN D_IN Detect Insertion Removal of Headphone Plug JACKDET Digital Microphone Stereo Input MICIN 5 MICBIAS A_OUT Bias Voltage for Electret Microphone 6 LAUX A_IN Left Channel Single Ended Auxiliary Input Biased at AVDD 2 7 CM A_OUT AVDD 2 V Common Mode Reference A 10 μF to 47 μF standard decoupling capacitor shoul...

Page 14: ...TA D_OUT ADC Serial Output Data 27 DAC_SDATA D_IN DAC Serial Input Data 28 BCLK D_IO Serial Data Port Bit Clock 29 LRCLK D_IO Serial Data Port Frame Clock 30 ADDR1 CDATA D_IN I2 C Address Bit 1 ADDR1 SPI Data Input CDATA 31 SDA COUT D_IO I2 C Data SDA This pin is a bidirectional open collector input output The line connected to this pin should have a 2 kΩ pull up resistor SPI Data Output COUT This...

Page 15: ...Load 18 0 2 4 6 8 10 12 14 16 STEREO OUTPUT POWER mW 08915 057 Figure 9 Headphone Amplifier Power vs Input Level 32 Ω Load 100 90 80 70 60 50 40 30 20 10 0 FREQUENCY NORMALIZED TO fS MAGNITUDE dBFS 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 08915 008 Figure 10 ADC Decimation Filter 64 Oversampling Normalized to fS Figure 11 Headphone Amplifier THD N vs Input Level 16 Ω Load 08915 058 Figure 12 Head...

Page 16: ... 0 50 0 45 0 10 0 08 0 06 0 04 0 02 0 0 02 0 04 0 06 0 08 0 10 FREQUENCY NORMALIZED TO fS MAGNITUDE dBFS 08915 011 Figure 16 DAC Interpolation Filter 64 Oversampling Double Rate Mode Normalized to fS Figure 17 ADC Decimation Filter Pass Band Ripple 128 Oversampling Normalized to fS 0 0 05 0 10 0 20 0 30 0 40 0 15 0 25 0 35 0 06 0 04 0 02 0 0 02 0 04 FREQUENCY NORMALIZED TO fS MAGNITUDE dBFS 08915 ...

Page 17: ... 50 28 25 26 00 23 75 21 50 19 25 17 00 14 75 12 50 10 25 8 00 5 75 3 50 1 25 1 00 3 25 5 50 7 75 10 00 12 25 GAIN dB 10 20 30 40 50 60 70 80 90 IMPEDANCE kΩ 08915 125 Figure 22 Input Impedance vs Gain for Analog Inputs 0 0 05 0 10 0 20 0 30 0 40 0 15 0 25 0 35 0 50 0 45 FREQUENCY NORMALIZED TO fS MAGNITUDE dBFS 08915 017 Figure 23 DAC Interpolation Filter Pass Band Ripple 128 Oversampling Normali...

Page 18: ... SCL CCLK ADDR0 CLATCH MICBIAS LOUTP LOUTN LHP MONOOUT RHP ROUTP ROUTN CAPLESS HEADPHONE OUTPUT EARPIECE SPEAKER EARPIECE SPEAKER CLOCK SOURCE THE INPUT CAPACITOR VALUE DEPENDS ON THE INPUT IMPEDANCE WHICH VARIES WITH THE VOLUME SETTING ADAU1961 10µF 10µF 10µF 0 1µF 10µF 10µF 0 1µF 0 1µF 0 1µF FROM VOLTAGE REGULATOR 1 8V TO 3 3V 9 1pF 2kΩ 2kΩ 1kΩ 1kΩ 49 9Ω 0 1µF 1 2nH 10µF 10µF 10µF 10µF 10µF 0891...

Page 19: ...S ON THE INPUT IMPEDANCE WHICH VARIES WITH THE VOLUME SETTING ADAU1961 10µF 10µF CM 10µF 10µF 10µF 0 1µF 10µF 10µF 0 1µF 0 1µF 9 1pF 0 1µF FROM VOLTAGE REGULATOR 1 8V TO 3 3V 1kΩ 1kΩ 49 9Ω 1 2nH 08915 059 VDD GND SINGLE ENDED ANALOG MICROPHONE OUTPUT VDD GND SINGLE ENDED ANALOG MICROPHONE OUTPUT LOUTP LOUTN LHP MONOOUT RHP ROUTP ROUTN CAPLESS HEADPHONE OUTPUT EARPIECE SPEAKER EARPIECE SPEAKER 0 1µ...

Page 20: ...AGE REGULATOR 1 8V TO 3 3V 1kΩ AUX RIGHT 10µF 1kΩ 49 9Ω BCLK 0 1µF 10µF 1 2nH 08915 060 22nF REXT 22nF REXT REXT 22nF INL INL INR INR OUTL OUTL OUTR OUTR SSM2306 CLASS D 2W STEREO SPEAKER DRIVER VDD VDD GND SD GND 2 5V TO 5 0V RIGHT SPEAKER LEFT SPEAKER LHP MONOOUT RHP CAPLESS HEADPHONE OUTPUT BCLK JACKDET MICIN GND L R SELECT DATA VDD CLK DIGITAL MICROPHONE GND L R SELECT DATA VDD CLK DIGITAL MIC...

Page 21: ...sing the ADCs An automatic level control ALC can also be implemented to keep the recording volume constant The ADCs and DACs are high quality 24 bit Σ Δ converters that operate at selectable 64 or 128 oversampling ratios The base sampling rate of the converters is set by the input clock rate and can be further scaled with the converter control register settings The converters can operate at sampli...

Page 22: ...os to 64 for these filters lowers power consumption with a minimal impact on performance See the Digital Filters section for specifications see the Typical Performance Characteristics section for graphs of these filters DIGITAL POWER SUPPLY The digital power supply for the ADAU1961 is generated from an internal regulator This regulator generates a 1 5 V supply internally The only external connecti...

Page 23: ...le through the control port Because all other registers require a valid master clock for reading and writing do not attempt to access any other register Any read or write is prohibited until the core clock enable bit COREN and the lock bit are both asserted To program the PLL during initialization or reconfiguration of the clock setting the following procedure must be followed 1 Power down the PLL...

Page 24: ...n using the PLL When using a direct clock the INFREQ 1 0 frequency should be set according to the MCLK pin clock rate and the desired base sampling frequency Table 11 Clock Control Register Register R0 Address 0x4000 Bits Bit Name Settings 3 CLKSRC 0 Direct from MCLK pin default 1 PLL clock 2 1 INFREQ 1 0 00 256 fS default 01 512 fS 10 768 fS 11 1024 fS 0 COREN 0 Core clock disabled default 1 Core...

Page 25: ... example if MCLK 12 MHz and fS 48 kHz then PLL required output 1024 48 kHz 49 152 MHz R N M 49 152 MHz 12 MHz 4 12 125 Common fractional PLL parameter settings for 44 1 kHz and 48 kHz sampling rates can be found in Table 15 and Table 16 The PLL outputs a clock in the range of 41 MHz to 54 MHz which should be taken into account when calculating PLL values and MCLK frequencies Table 14 PLL Control R...

Page 26: ...PLL Output 49 152 MHz 1024 fS MCLK Input MHz Input Divider X Integer R Denominator M Numerator N R2 PLL Control Setting Hex 8 1 6 125 18 0x007D 0012 3101 12 1 4 125 12 0x007D 000C 2101 13 1 3 1625 1269 0x0659 04F5 1901 14 4 2 6 75 62 0x004B 003E 3301 19 2 2 5 25 3 0x0019 0003 2B01 19 68 2 4 205 204 0x00CD 00CC 2301 19 8 2 4 825 796 0x0339 031C 2301 24 2 4 125 12 0x007D 000C 2301 26 2 3 1625 1269 0...

Page 27: ... inputs are biased at AVDD 2 Unused input pins should be connected to CM Each of the six analog inputs has individual gain controls boost or cut The input signals are mixed and routed to an ADC The mixed input signals can also bypass the ADCs and be routed directly to the playback mixers Left channel inputs are mixed before the left ADC however it is possible to route the mixed analog signal aroun...

Page 28: ...tion the signal connects to the inverting input of the PGA LINN and or RINN as shown in Figure 33 LEFT MICROPHONE LEFT PGA LDBOOST 1 0 MUTE 0dB 20dB 12dB TO 35 25dB RIGHT MICROPHONE RIGHT PGA RDBOOST 1 0 MUTE ADAU1961 0dB 20dB 12dB TO 35 25dB LINN LINP RINP MICBIAS RINN CM 2kΩ 2kΩ 08915 053 Figure 33 Stereo Single Ended Microphone Configuration Analog Line Inputs Line input signals can be accepted...

Page 29: ... input level is measured after the differential amplifier which corresponds to 6 dBFS at each pin JDFUNC 1 0 DIGITAL MICROPHONE INTERFACE LEFT CHANNEL RIGHT CHANNEL TO JACK DETECTION CIRCUIT JACKDET MICIN RIGHT ADC LEFT ADC R19 ADC CONTROL INSEL R2 DIGITAL MICROPHONE JACK DETECTION CONTROL Signal levels above the full scale value cause the ADCs to clip Digital ADC Volume Control The digital ADC vo...

Page 30: ...erall sound quality If the value is too fast the ALC overreacts to very short transients causing audible gain pumping effects which sounds worse than using a moderate value that allows brief periods of clipping on transients A typical setting for music recording is 384 ms A typical setting for voice recording is 24 ms ALCHOLD 3 0 These bits set the ALC hold time When the output signal falls below ...

Page 31: ...bination of a timeout period and hysteresis The timeout period is set to 250 ms so the signal must consistently be below the threshold for 250 ms before the noise gate operates Hysteresis is used so that the threshold for coming out of the mute state is 6 dB higher than the threshold for going into the mute state There are four operating modes for the noise gate Noise Gate Mode 0 see Figure 39 is ...

Page 32: ...is the same as Mode 2 except that at the end of the PGA fade gain interval a digital mute is performed In general this mode is the best sounding mode because the audible effect of the digital hard mute is reduced by the fact that the gain has already faded to a low level before the mute occurs THRESHOLD INPUT ANALOG GAIN DIGITAL MUTE OUTPUT INTERNAL NOISE GATE ENABLE SIGNAL 250ms MIN GAIN 100ms 08...

Page 33: ...ins are biased at AVDD 2 With a 0 dBFS digital input and AVDD 3 3 V the full scale output level is 920 mV rms Signals are inverted through the mixers and volume controls The result of this inversion is that the polarity of the differential outputs and the headphone outputs is preserved The single ended mono output is inverted The DACs are noninverting Routing Flexibility The playback path contains...

Page 34: ...tput MOMODE 1 headphone output R29 LHPVOL 5 0 Desired volume for LHP output LHPM 1 unmute left headphone output R30 HPMODE 1 headphone output RHPVOL 5 0 Desired volume for RHP output RHPM 1 unmute right headphone output Headphone Output Power Up Power Down Sequencing To prevent pops when turning on the headphone outputs the user must wait at least 4 ms to unmute these outputs after enabling the he...

Page 35: ...r up precharge circuitry is enabled to suppress pops and clicks After power up the precharge circuitry can be put into a low power mode using the POPMODE bit in Register R34 playback pop click suppression register Address 0x4028 The volume controls for these outputs range from 57 dB to 6 dB Slew can be applied to all the playback volume controls using the ASLEW 1 0 bits in Register R34 playback po...

Page 36: ...the word length at each subaddress so the subaddress does not need to be specified manually for each address in a burst write The subaddresses are autoincremented by 1 following each read or write of a data word regardless of whether there is a valid register word at that address Address holes in the register map can be written to or read from without consequence In the ADAU1961 these address hole...

Page 37: ...crement mode one of two actions is taken In read mode the ADAU1961 outputs the highest subaddress register contents until the master device issues a no acknowledge indicating the end of a read A no acknowledge condition is where the SDA line is not pulled low on the ninth clock pulse on SCL If the highest subaddress location is reached while in write mode the data for the invalid byte is not loade...

Page 38: ...1 Figure 53 shows the format of a burst mode read sequence This figure shows an example of a read from sequential single byte registers The ADAU1961 increments its subaddress register after every byte because the requested subaddress corresponds to a register or memory area with a 1 byte word length The ADAU1961 always decodes the subaddress and sets the auto increment circuit so that the address ...

Page 39: ... W bit This bit determines whether the communication is a read Logic Level 1 or a write Logic Level 0 This format is shown in Table 21 Table 21 ADAU1961 SPI Address and Read Write Byte Format Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 0 0 0 0 0 0 0 R W Subaddress The 16 bit subaddress word is decoded into a location in one of the registers This subaddress is the location of the appropriate re...

Page 40: ...LK frame The LRCLK in TDM mode can be input to the ADAU1961 either as a 50 duty cycle clock or as a bit wide pulse When the LRCLK is set as a pulse a 47 pF capacitor should be connected between the LRCLK pin and ground see Figure 56 This capacitor is necessary in both master and slave modes to properly align the LRCLK signal to the serial data stream LRCLK ADAU1961 BCLK 08915 071 47pF Figure 56 LR...

Page 41: ...to 24 Bits per Channel LRCLK LEFT CHANNEL RIGHT CHANNEL BCLK SDATA MSB LSB MSB LSB 1 fS 08915 042 Figure 59 Right Justified Mode 16 Bits to 24 Bits per Channel LRCLK BCLK SDATA SLOT 0 SLOT 2 32 BCLKs MSB MSB 1 MSB 2 128 BCLKs SLOT 1 SLOT 3 LRCLK BCLK SDATA 08915 043 Figure 60 TDM 4 Mode LRCLK SLOT 0 SLOT 1 SLOT 2 SLOT 3 CH 0 BCLK SDATA 32 BCLKs MSB TDM 08915 044 Figure 61 TDM 4 Mode with Pulse Wor...

Page 42: ...ould consist of a 1 2 nH inductor and a 9 1 pF capacitor in series between AVDD and ground as shown in Figure 63 AVDD AVDD 0 1µF 0 1µF 9 1pF 1 2nH 10µF 08915 04 TOP POWER GROUND BOTTOM COPPER SQUARES VIAS 9 Figure 63 GSM Filter on the Analog Supply Pins GROUNDING A single ground plane should be used in the application layout Components in an analog signal path should be placed away from digital si...

Page 43: ...Reserved ADCPOL HPF DMPOL DMSW INSEL ADCEN 1 0 00010000 R20 0x401A Left digital vol LADVOL 7 0 00000000 R21 0x401B Right digital vol RADVOL 7 0 00000000 R22 0x401C Play Mixer Left 0 Reserved MX3RM MX3LM MX3AUXG 3 0 MX3EN 00000000 R23 0x401D Play Mixer Left 1 MX3G2 3 0 MX3G1 3 0 00000000 R24 0x401E Play Mixer Right 0 Reserved MX4RM MX4LM MX4AUXG 3 0 MX4EN 00000000 R25 0x401F Play Mixer Right 1 MX4G...

Page 44: ...ore clock disabled default 1 core clock enabled R1 PLL Control 16 386 0x4002 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 M 15 8 1 M 7 0 2 N 15 8 3 N 7 0 4 Reserved R 3 0 X 1 0 Type 5 Reserved Lock PLLEN Table 27 PLL Control Register Byte Bits Bit Name Description 0 7 0 M 15 8 PLL denominator MSB This value is concatenated with M 7 0 to make up a 16 bit number 1 7 0 M 7 0 PLL denominator...

Page 45: ...ider Setting Value of X 00 1 default 01 2 10 3 11 4 4 0 Type Type of PLL When set to integer mode the values of M and N are ignored 0 integer default 1 fractional 5 1 Lock PLL lock This read only bit is flagged when the PLL has finished locking 0 PLL unlocked default 1 PLL locked 5 0 PLLEN PLL enable 0 PLL disabled default 1 PLL enabled Downloaded from Elcodis com electronic components distributor...

Page 46: ...d R4 Record Mixer Left Mixer 1 Control 0 16 394 0x400A This register controls the gain of single ended inputs for the left channel record path The left channel record mixer is referred to as Mixer 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved LINPG 2 0 LINNG 2 0 MX1EN Table 29 Record Mixer Left Mixer 1 Control 0 Register Bits Bit Name Description 6 4 LINPG 2 0 Gain for a left channel ...

Page 47: ...cord Mixer Left Mixer 1 Control 1 Register Bits Bit Name Description 4 3 LDBOOST 1 0 Left channel differential PGA input gain boost input to Mixer 1 The left differential input uses the LINP positive signal and LINN negative signal pins Setting Gain Boost 00 Mute default 01 0 dB 10 20 dB 11 Reserved 2 0 MX1AUXG 2 0 Left single ended auxiliary input gain from the LAUX pin in the record path input t...

Page 48: ...Bit Name Description 6 4 RINPG 2 0 Gain for a right channel single ended input from the RINP pin input to Mixer 2 Setting Gain 000 Mute default 001 12 dB 010 9 dB 011 6 dB 100 3 dB 101 0 dB 110 3 dB 111 6 dB 3 1 RINNG 2 0 Gain for a right channel single ended input from the RINN pin input to Mixer 2 Setting Gain 000 Mute default 001 12 dB 010 9 dB 011 6 dB 100 3 dB 101 0 dB 110 3 dB 111 6 dB 0 MX2...

Page 49: ...B 101 0 dB 110 3 dB 111 6 dB R8 Left Differential Input Volume Control 16 398 0x400E This register enables the differential path and sets the volume control for the left differential PGA input Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LDVOL 5 0 LDMUTE LDEN Table 33 Left Differential Input Volume Control Register Bits Bit Name Description 7 2 LDVOL 5 0 Left channel differential PGA input volu...

Page 50: ...default 1 unmute 0 RDEN Right differential PGA enable When enabled the RINP and RINN pins are used as a full differential pair When disabled these two pins are configured as two single ended inputs with the signals routed around the PGA 0 disabled default 1 enabled R10 Record Microphone Bias Control 16 400 0x4010 This register controls the MICBIAS pin settings for biasing electret type analog micr...

Page 51: ... small signals from excessive amplification Setting Maximum ALC Gain 000 12 dB default 001 6 dB 010 0 dB 011 6 dB 100 12 dB 101 18 dB 110 24 dB 111 30 dB 2 0 ALCSEL 2 0 ALC select These bits set the channels that are controlled by the ALC When set to right only the ALC responds only to the right channel input and controls the gain of the right PGA amplifier only When set to left only the ALC respo...

Page 52: ... 0001 5 34 ms 0010 10 68 ms 0011 21 36 ms 0100 42 72 ms 0101 85 44 ms 0110 170 88 ms 0111 341 76 ms 1000 683 52 ms 1001 1 367 sec 1010 2 7341 sec 1011 5 4682 sec 1100 10 936 sec 1101 21 873 sec 1110 43 745 sec 1111 87 491 sec 3 0 ALCTARG 3 0 ALC target The ALC target sets the desired ADC input level The PGA gain is adjusted by the ALC to reach this target level The recommended target level is betw...

Page 53: ...ms 0101 192 ms 0110 384 ms 0111 768 ms 1000 1 54 sec 1001 3 07 sec 1010 6 14 sec 1011 12 29 sec 1100 24 58 sec 1101 49 15 sec 1110 98 30 sec 1111 196 61 sec 3 0 ALCDEC 3 0 ALC decay time The decay time sets how fast the ALC increases the PGA gain after a decrease in input level below the target A typical setting for music recording is 24 58 seconds and a typical setting for voice recording is 1 54...

Page 54: ...it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DITHEN Reserved LRMOD BPOL LRPOL CHPF 1 0 MS Table 40 Serial Port Control 0 Register Bits Bit Name Description 7 DITHEN Dither enable is applicable only for 16 bit data width modes 0 disabled default 1 enabled 5 LRMOD LRCLK mode sets the LRCLK for either a 50 duty cycle or a pulse The pulse mode should be at least 1 BCLK wide 0 50 duty cycle default 1 pulse...

Page 55: ...default 001 32 010 48 011 128 100 256 101 Reserved 110 Reserved 111 Reserved 4 ADTDM ADC serial audio data channel position in TDM mode 0 left first default 1 right first 3 DATDM DAC serial audio data channel position in TDM mode 0 left first default 1 right first 2 MSBP MSB position in the LRCLK frame 0 MSB first default 1 LSB first 1 0 LRDEL 1 0 Data delay from LRCLK edge in BCLK units Setting D...

Page 56: ... DACs operate at the sampling rate set in this register The converter rate selected is a ratio of the base sampling rate fS The base sampling rate is determined by the operating frequency of the core clock The serial port mirrors the converter sampling rates set in this register Setting Sampling Rate Base Sampling Rate fS 48 kHz 000 fS 48 kHz base default 001 fS 6 8 kHz 010 fS 4 12 kHz 011 fS 3 16...

Page 57: ... BCLK is master at 128 fS and ADC_SDATA is expected to have left and right channels interleaved 0 digital microphone inputs off ADCs enabled default 1 digital microphone inputs enabled ADCs off 1 0 ADCEN 1 0 ADC enable Setting ADCs Enabled 00 Both off default 01 Left on 10 Right on 11 Both on R20 Left Input Digital Volume 16 410 0x401A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LADVOL 7 0 Tab...

Page 58: ...back Mixer Left Mixer 3 Control 0 16 412 0x401C Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved MX3RM MX3LM MX3AUXG 3 0 MX3EN Table 47 Playback Mixer Left Mixer 3 Control 0 Register Bits Bit Name Description 6 MX3RM Mixer input mute Mutes the right DAC input to the left channel playback mixer Mixer 3 0 muted default 1 unmuted 5 MX3LM Mixer input mute Mutes the left DAC input to the left c...

Page 59: ... converters and gain can be applied before the left playback mixer Mixer 3 Setting Gain 0000 Mute default 0001 15 dB 0010 12 dB 0011 9 dB 0100 6 dB 0101 3 dB 0110 0 dB 0111 3 dB 1000 6 dB 3 0 MX3G1 3 0 Bypass gain control The signal from the left channel record mixer Mixer 1 bypasses the converters and gain can be applied before the left playback mixer Mixer 3 Setting Gain 0000 Mute default 0001 1...

Page 60: ...nnel playback mixer Mixer 4 0 muted default 1 unmuted 5 MX4LM Mixer input mute Mutes the left DAC input to the right channel playback mixer Mixer 4 0 muted default 1 unmuted 4 1 MX4AUXG 3 0 Mixer input gain Controls the right channel auxiliary input gain to the right channel playback mixer Mixer 4 Setting Gain 0000 Mute default 0001 15 dB 0010 12 dB 0011 9 dB 0100 6 dB 0101 3 dB 0110 0 dB 0111 3 d...

Page 61: ...111 3 dB 1000 6 dB R26 Playback L R Mixer Left Mixer 5 Line Output Control 16 416 0x4020 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved MX5G4 1 0 MX5G3 1 0 MX5EN Table 51 Playback L R Mixer Left Mixer 5 Line Output Control Register Bits Bit Name Description 4 3 MX5G4 1 0 Mixer input gain boost The signal from the right channel playback mixer Mixer 4 can be enabled and boosted in the play...

Page 62: ...oost 00 Mute default 01 0 dB output 6 dB gain on each of the two inputs 10 6 dB output 0 dB gain on each of the two inputs 11 Reserved 0 MX6EN Mixer 6 enable 0 disabled default 1 enabled R28 Playback L R Mixer Mono Output Mixer 7 Control 16 418 0x4022 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved MX7 1 0 MX7EN Table 53 Playback L R Mixer Mono Output Mixer 7 Control Register Bits Bit Nam...

Page 63: ...nabled 0 disabled default 1 enabled R30 Playback Headphone Right Volume Control 16 420 0x4024 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RHPVOL 5 0 RHPM HPMODE Table 55 Playback Headphone Right Volume Control Register Bits Bit Name Description 7 2 RHPVOL 5 0 Headphone volume control for right channel RHP output Each 1 bit step corresponds to a 1 dB increase in volume See Table 72 for a comple...

Page 64: ...akers set this bit to 1 headphone output 0 line output default 1 headphone output R32 Playback Line Output Right Volume Control 16 422 0x4026 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ROUTVOL 5 0 ROUTM ROMODE Table 57 Playback Line Output Right Volume Control Register Bits Bit Name Description 7 2 ROUTVOL 5 0 Line output volume control for right channel ROUTN and ROUTP outputs Each 1 bit ste...

Page 65: ...it 2 Bit 1 Bit 0 Reserved POPMODE POPLESS ASLEW 1 0 Reserved Table 59 Playback Pop Click Suppression Register Bits Bit Name Description 4 POPMODE Pop suppression circuit power saving mode The pop suppression circuits charge faster in normal operation however after they are charged they can be put into low power operation 0 normal default 1 low power 3 POPLESS Pop suppression disable The pop suppre...

Page 66: ...is filter enable The de emphasis filter is designed for use with a sampling rate of 44 1 kHz only 0 disabled default 1 enabled 1 0 DACEN 1 0 DAC enable Setting DACs Enabled 00 Both off default 01 Left on 10 Right on 11 Both on R37 DAC Control 1 16 427 0x402B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LDAVOL 7 0 Table 62 DAC Control 1 Register Bits Bit Name Description 7 0 LDAVOL 7 0 Controls ...

Page 67: ...ll down resistors set the serial port signals to a defined state when the signal source becomes three state Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADCSDP 1 0 DACSDP 1 0 LRCLKP 1 0 BCLKP 1 0 Table 64 Serial Port Pad Control Register Bits Bit Name Description 7 6 ADCSDP 1 0 ADC_SDATA pad pull up pull down configuration Setting Configuration 00 Pull up 01 Reserved 10 None default 11 Pull dow...

Page 68: ...0 Pull up 01 Reserved 10 None default 11 Pull down 3 2 SCLP 1 0 SCL CCLK pad pull up pull down configuration Setting Configuration 00 Pull up 01 Reserved 10 None default 11 Pull down 1 0 SDAP 1 0 SDA COUT pad pull up pull down configuration Setting Configuration 00 Pull up 01 Reserved 10 None default 11 Pull down R41 Control Port Pad Control 1 16 432 0x4030 With IOVDD set to 3 3 V the low and high...

Page 69: ...pped samples due to jitter from the serial ports in slave mode Disabling and reenabling certain subsystems in the device that is the ADCs serial ports and DACs during operation can cause the associated dejitter circuits to fail As a result audio data fails to be output to the next subsystem in the device When the serial ports are in master mode the dejitter circuit can be bypassed by setting the d...

Page 70: ...01001 18 75 101010 19 5 101011 20 25 101100 21 101101 21 75 101110 22 5 101111 23 25 110000 24 110001 24 75 110010 25 5 Binary Value Volume Setting dB 110011 26 25 110100 27 110101 27 75 110110 28 5 110111 29 25 111000 30 111001 30 75 111010 31 5 111011 32 25 111100 33 111101 33 75 111110 34 5 111111 35 25 Table 70 R14 Noise Gate Threshold Binary Value Noise Gate Threshold dB 00000 76 5 00001 75 0...

Page 71: ...5 00101010 15 75 00101011 16 125 00101100 16 5 00101101 16 875 00101110 17 25 00101111 17 625 Binary Value Volume Attenuation dB 00110000 18 00110001 18 375 00110010 18 75 00110011 19 125 00110100 19 5 00110101 19 875 00110110 20 25 00110111 20 625 00111000 21 00111001 21 375 00111010 21 75 00111011 22 125 00111100 22 5 00111101 22 875 00111110 23 25 00111111 23 625 01000000 24 01000001 24 375 010...

Page 72: ...11 52 125 10001100 52 5 10001101 52 875 10001110 53 25 10001111 53 625 10010000 54 Binary Value Volume Attenuation dB 10010001 54 375 10010010 54 75 10010011 55 125 10010100 55 5 10010101 55 875 10010110 56 25 10010111 56 625 10011000 57 10011001 57 375 10011010 57 75 10011011 58 125 10011100 58 5 10011101 58 875 10011110 59 25 10011111 59 625 10100000 60 10100001 60 375 10100010 60 75 10100011 61...

Page 73: ...7 11101001 87 375 11101010 87 75 11101011 88 125 11101100 88 5 11101101 88 875 11101110 89 25 11101111 89 625 11110000 90 11110001 90 375 11110010 90 75 Binary Value Volume Attenuation dB 11110011 91 125 11110100 91 5 11110101 91 875 11110110 92 25 11110111 92 625 11111000 93 11111001 93 375 11111010 93 75 11111011 94 125 11111100 94 5 11111101 94 875 11111110 95 25 11111111 95 625 Table 72 R29 th...

Page 74: ...20 100110 19 100111 18 101000 17 101001 16 101010 15 101011 14 101100 13 101101 12 101110 11 101111 10 110000 9 110001 8 110010 7 110011 6 110100 5 110101 4 110110 3 110111 2 111000 1 111001 0 111010 1 111011 2 111100 3 111101 4 111110 5 111111 6 Downloaded from Elcodis com electronic components distributor ...

Page 75: ...ip Scale Package LFCSP_VQ CP 32 4 ADAU1961WBCPZ R7 40 C to 105 C 32 Lead Lead Frame Chip Scale Package LFCSP_VQ 7 Tape and Reel CP 32 4 ADAU1961WBCPZ RL 40 C to 105 C 32 Lead Lead Frame Chip Scale Package LFCSP_VQ 13 Tape and Reel CP 32 4 1 Z RoHS Compliant Part 2 W Qualified for Automotive Applications AUTOMOTIVE PRODUCTS The ADAU1961 models are available with controlled manufacturing to support ...

Page 76: ...e 76 of 76 NOTES 2010 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D08915 0 10 10 0 Downloaded from Elcodis com electronic components distributor ...

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