ADAU1961
Rev. 0 | Page 41 of
76
LRCLK
BCLK
SDATA
MSB
LSB
MSB
LSB
LEFT CHANNEL
RIGHT CHANNEL
1/
f
S
08
91
5-
0
40
Figure 57. I
2
S Mode—16 Bits to 24 Bits per Channel
LRCLK
LEFT CHANNEL
RIGHT CHANNEL
BCLK
SDATA
MSB
LSB
MSB
LSB
1/
f
S
0
89
15
-0
41
Figure 58. Left-Justified Mode—16 Bits to 24 Bits per Channel
LRCLK
LEFT CHANNEL
RIGHT CHANNEL
BCLK
SDATA
MSB
LSB
MSB
LSB
1/
f
S
08
91
5-
04
2
Figure 59. Right-Justified Mode—16 Bits to 24 Bits per Channel
LRCLK
BCLK
SDATA
SLOT 0
SLOT 2
32 BCLKs
MSB
MSB – 1
MSB – 2
128 BCLKs
SLOT 1
SLOT 3
LRCLK
BCLK
SDATA
08
91
5-
0
43
Figure 60. TDM 4 Mode
LRCLK
SLOT 0
SLOT 1
SLOT 2
SLOT 3
CH
0
BCLK
SDATA
32 BCLKs
MSB TDM
08
915
-04
4
Figure 61. TDM 4 Mode with Pulse Word Clock
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