AD9695 External Trigger Quick Start Guide
SOFTWARE NEEDED
VisualAnalog (VA) (http://www.analog.com/en/design-center/interactive-design-tools/visualanalog.html )
Analysis | Control | Eval uation (ACE) (http://www.analog.com/en/design-center/evaluation-hardware-and-
software/ace-software.html)
Appropriate .bin FPGA file (supplied separately)
Documents are available at http://www.analog.com.
For any questions, please send an email to [email protected].
TESTING
(Note: Though AD9695 is mentioned in this document, this procedure also applies to the AD9689 and AD9208)
1.
Setup the AD9695 evaluation board as described in the AD9695 User Guide. Verify that the evaluation board is
converting and processing data normally as specified in the User Guide.
2.
Additionally, hardware connections to the SMA connectors SMA1 J5 (Trigger Input Pin) and SMA2 J6 (Ready Status
Output Pin) are needed (See figure 1). The FPGA will send an output signal on SMA2 J6 when the FPGA is ready for
another capture – see Figure 2 below.
Figure 2: Time Capture of Ready Pin Output
A pulse input on SMA1 J5 will signal to the FPGA to start a capture. The trigger requires an active high pulse width that is
longer than the FPGA internal memory clock. See Figure 3 below for an example of a pulsing signal that might be sent.
