manualshive.com logo in svg

Analog Devices AD9656, Manual

Share
Download
Analog Devices AD9656 Manual Download Page 11

 

Rev 20 Feb 2014 17:53 | Page 11

checkbox. The capture control fields will be enabled.
Select:

GTX RX Equalization: 6

●

Encode: 125MSPS (default configuration)

●

Number of lanes: 2 Lanes (At least 2 lanes are required for 125MSPS. The single lane bitrate at

●

125MSPS would exceed the driver and FPGA capabilities.)
Leave the other checkboxes unchecked.

●

Though the AD9656 supports a wide variety of converter/lane/sample rate configurations, the
software supports only the configurations in the software menu as an out-of-the-box functional kit. If
other sample rates or configurations are required, an additional external clock is likely needed.

Figure 10. VisualAnalog ADC Data Capture Settings Window, Device Tab

8. VisualAnalog is now setup to work with the AD9656EBZ in the default configuration. Other
VisualAnalog features and capture settings are documented in the 

AN-905 Application Note

,

VisualAnalog Converter Evaluation Tool Version 1.0 User Manual.

Evaluation And Test

Setting up the SPI Controller Software

After the ADC data capture board setup is complete, set up the SPI controller software using the
following procedure:

Open the SPI controller software by going to the Start menu or by double-clicking the

1.

Summary of Contents for AD9656

Page 1: ...support circuitry required to operate the ADC in its various modes and configurations The application software used to interface with the device is also described The AD9656 data sheet provides additional information and should be consulted when using the evaluation board Documents and software tools are available at AD9656 and www analog com hsadcevalboard For additional information or questions ...

Page 2: ...erence off board reference VisualAnalog and SPIController software interfaces Helpful Documents AD9656 data sheet High speed ADC FIFO evaluation kit HSC ADC EVALEZ HSC ADC EVALEZ Wiki Guide http wiki analog com resources eval hsc adc evald AN 905 Application Note VisualAnalog Converter Evaluation Tool Version 1 0 User Manual AN 878 Application Note High Speed ADC SPI Control Software AN 877 Applic...

Page 3: ...n the ADC evaluation board confirm that the jumpers are installed as shown in Figure 2 2 The AD9656EBZ can be powered in one of three ways The default is to have the AD9656EBZ 3 obtain its power from the HSC ADC EVALEZ through the FMC connector For this configuration jumper pin 1 to pin 2 on both P101 and P103 on the AD9656EBZ The other power configurations will be described in the Power Supplies ...

Page 4: ... and then place them in their desired positions Alternatively the AD9656EBZ can obtain its power from the wall mountable 6V 2A switching power supply For this mode P101 and P103 both need to have pin 2 tied to pin 3 Connect the supply to a 100V ac to 240V ac 47Hz to 63Hz wall outlet The output from the supply is provided through a 2 1mm inner diameter jack that connects to the printed circuit boar...

Page 5: ...ide ratios of 1 through 8 to facilitate usage with higher frequency clocks When using the internal divider and a higher input clock frequency remove CR301 to preserve the slew rate of the clock signal The AD9656EBZ board is set up to be clocked through the transformer coupled input network from the 125MHz crystal oscillator Y801 If an external clock source is desired remove C302 optionally and Jum...

Page 6: ...hoose the ADC s internal reference connect Pin 3 DUT_SENSE to Pin 5 GND as shown in Figure 2 The default value of the internal reference is 1 V SPI Register 0x18 Bits 7 6 can be used to program the internal reference voltage to values from 1 V to 1 4 V in 0 1 V increments Register control is accomplished with SPIController software which is discussed below in the Setting up the SPI Controller Soft...

Page 7: ...og com pub adispi A2DComponents Install SPIController_Setup exe Run these installers on the PC that is connected to the evaluation setup before proceeding After configuring the board hardware set up the ADC data capture using the following steps Start VisualAnalog on the connected PC The appropriate part type should be listed in the status 1 bar of the VisualAnalog New Canvas window Select the tem...

Page 8: ...program the FPGA see Figure 4 If this message appears click Yes and the window will close Figure 4 VisualAnalog Default Configuration Message To view the canvas and associated functional blocks click the Expand Display button located on 3 the bottom right corner of the window see Figure 5 to see what is shown in Figure 6 Figure 5 VisualAnalog Window Toolbar Collapsed Display ...

Page 9: ...play 5 In the ADC Data Capture Settings Window General Tab select AD9656 to be the device enter the sample clock frequency 125 is the default value as shown in Figure 8 The sample frequency entered here is used for scaling of frequency values in test results and graphs In the Output Data field the channels to be tested are selected as well as the FFT capture depth Length Note that the total of the...

Page 10: ... Browse button to navigate to the FPGA program file for the AD9656 The default installation location and filename will be similar to C Program Files Analog Devices VisualAnalog Hardware HADv6 AD9656_hadv6fmc mcs Push the program button Figure 9 VisualAnalog ADC Data Capture Settings Window Capture Board Tab 7 In the ADC Data Capture Settings Window Device Tab check the Enable Data Capture Controls...

Page 11: ... of the box functional kit If other sample rates or configurations are required an additional external clock is likely needed Figure 10 VisualAnalog ADC Data Capture Settings Window Device Tab 8 VisualAnalog is now setup to work with the AD9656EBZ in the default configuration Other VisualAnalog features and capture settings are documented in the AN 905 Application Note VisualAnalog Converter Evalu...

Page 12: ...indow to determine which configuration is loaded If necessary choose Cfg Open from the File menu and select the appropriate file based on your part type Note that the CHIP ID 1 box should be filled to indicate whether the correct SPI controller configuration file is loaded see Figure 11 Figure 11 SPI Controller CHIP ID 1 Box Click the New DUT button in the SPIController window see Figure 12 2 ...

Page 13: ...divider use the drop down box to select the correct clock divide ratio if necessary If there is any interruption of the ADC clock during power up or during operation a Digital Reset may be needed to re initialize the ADC Figure 14 For additional information refer to the data sheet the AN 878 Application Note High Speed ADC SPI Control Software and the AN 877 Application Note Interfacing to High Sp...

Page 14: ...Rev 20 Feb 2014 17 53 Page 14 Figure 13 SPI Controller CLOCK DIVIDE B Box ...

Page 15: ...wer Mode Digital Reset Selection In the ADCBase1 tab of the SPIController window set the number of lanes the AD9656 will be 4 configured to Note that the number of lanes selected here must match the settings made in VisualAnalog as shown in Step 7 Figure 10 above ...

Page 16: ...ure 16 to set up the part in the desired mode The ADCBase0 tab settings affect the entire part whereas the settings on the ADC A through ADC D tabs each affect the selected channel only See the data sheet the AN 878 Application Note High Speed ADC SPI Control Software and the AN 877 Application Note Interfacing to High Speed ADCs via SPI for additional information on the available settings ...

Page 17: ...he VisualAnalog toolbar see 7 Figure 17 Figure 17 Run Continuous Run Buttons Encircled in Red in VisualAnalog Toolbar Collapsed Display Adjusting the Amplitude of the Input Signal The next step is to adjust the amplitude of the input signal for each channel as follows Adjust the amplitude of the input signal so that the fundamental is at the desired level Examine 1 the Fund Power reading in the le...

Page 18: ...w 0x00 the ADC is not powered up or SPI communication is not working Check that there is correct power to the AD9656EBZ board and to the HSC ADC EVALEZ Check that the USB cable is properly connected from the PC to the HSC ADC EVALEZ The LED on the VisualAnalog ADCDataCapture block should be green If it is red push the USB button on the same block to refresh the connection If the FFT plot appears a...

Page 19: ...on board is securely connected to the HSC ADC EVALEZ board Make sure that the correct FPGA program was installed by clicking the Settings icon in the ADC Data Capture block in VisualAnalog Then select the FPGA tab and verify that the proper FPGA mcs file one containing AD9656 in the filename is selected for the part Make sure that the FPGA has been programmed by verifying that the CONFIG_DONE LED ...

Reviews:

No comments

Brands by name

Popular brands

Load more brands