Analog Devices AD9522 Series, User Manual

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UG-077 Evaluation Board User Guide
Rev. 0 | Page 14 of 16
AD9522 PLL LOOP FILTER
The AD9522 PLL requires an external loop filter whose compo-
nents are tailored for different applications. The third-order
passive configuration shown in Figure 27 usually offers the best
performance for many applications and is the one found on the
evaluation board.
CLK/CLK
EXTERNAL
VCO / VCXO
CHARGE
PUMP
CP
C1
C2
C3
R1
R2
AD9522
08747-
024
Figure 27. AD9522 PLL Loop Filter
The default loop filter on the AD9522 evaluation board is
optimized for reference clock cleanup. It has a flat transfer
function with peaking <0.1 dB and loop bandwidths from
0.5 kHz to 10 kHz. In most of these applications, the phase
detector is run at 1 MHz or less.
In the example in the Quick Start Guide to the AD9522 PLL
section, the default loop filter shown in Table 2 results in a PLL
with a loop bandwidth of 2.2 kHz, 80° of phase margin, and
0.05 dB of peaking. The charge pump current for this example
is 1.2 mA.
For clock generation applications in which the reference clock is
relatively low jitter, the high loop bandwidth (BW) loop filter
shown in Table 2 is a better choice. Typical phase detector
frequencies for these applications are 10 MHz to 100 MHz,
and typical loop bandwidths for this loop filter are 50 kHz to
500 kHz, depending on the configuration.
The user should not consider these recommendations as a
substitute for using ADIsimCLK™ to determine the best loop
filter for a given application. ADIsimCLK is a free program
that can help with the design and exploration of the capabilities
and features of the AD9522, including the design of the PLL
loop filter. The evaluation software CD includes a sample
ADIsimCLK file that includes the AD9522 default loop filter
titled AD9522EvalBoardExample_148p5MHz.clk. ADIsimCLK
Version 1.3 includes specific support for the AD9522. However,
tTherefore, ADIsimCLK Version 1.2 can also be used for modeling
the AD9522 loop filter by selecting the corresponding version of
the AD9516. ADIsimCLK is available aTable 2 shows the correspondence between the components
shown in Figure 27 and those on the evaluation board, as well
as the default values.
Table 2. AD9522 Evaluation Board Default Loop Filter Values
ADIsimCLK
Evaluation Board
Location Clock Cleanup
(Default) High
Loop BW
C1 C25 1500 pF 62 pF
R1 R5 2.1 kΩ 820 Ω
C2 C22 4.7 μF 240 nF
R2 R2 3 kΩ 390 Ω
C3 C31 2200 pF 33 pF