AD9510/PCB
Rev. 0 | Page 19 of 28
Clock Distribution Section
The eight clock outputs are configured in the clock distribution section (Figure 25) of the main interface window. Here you can set each
divider and phase settings, the fine delay control settings, the output level, and power down settings.
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Figure 25. Clock Distribution Section, Main Interface Window
The output frequency of the eight outputs is calculated from the divider settings and the specified input clock frequency. It is then
displayed on the right-hand side of the clock distribution section. If the calculated output frequency exceeds the rated driver frequency,
the displayed frequency appears in red.
