UG-191
AD9286-500EBZ User Guide
Rev. A | Page 8 of 24
5.
Click the
Run
button in the
VisualAnalog
toolbar (see
09346-
011
Figure 11. Run Button in VisualAnalog Toolbar, Collapsed Display
Adjusting the Amplitude of the Input Signal
The next step is to adjust the amplitude of the input signal for
each channel as follows:
1.
Adjust the amplitude of the input signal so that the funda-
mental is at the desired level (examine the
Fund Power
reading in the left panel of the
VisualAnalog Graph -
FFT
window). See Figure 12.
09346-
012
Figure 12. Graph Window of VisualAnalog
2.
Repeat this procedure for Channel B.
3.
Click the disk icon within the
Graph
window to save the
performance plot data as a .csv formatted file.
Troubleshooting Tips
If the FFT plot appears abnormal, do the following:
•
If you see a normal noise floor when you disconnect the
signal generator from the analog input, be sure you are not
overdriving the ADC. Reduce the input level, if necessary.
•
In VisualAnalog, click the
Settings
button in the
Input
Formatter
block. Check that
Number Format
is set to the
correct encoding (offset binary by default). Repeat for the
other channel.
If the FFT appears normal but the performance is poor, check
the following:
•
Make sure an appropriate filter is used on the analog input.
•
Make sure the signal generators for the clock and the
analog input are clean (low phase noise).
•
Change the analog input frequency slightly if noncoherent
sampling is being used.
•
Make sure the SPI configuration file matches the product
being evaluated.
If the FFT window remains blank after
Run
is clicked, do the
following:
•
Make sure the evaluation board is securely connected to
the
•
Make sure the FPGA has been programmed by verifying
that the
DONE
board. If this LED is not illuminated, make sure
the U4 switch on the
board is in the
correct position for USB configuration.
•
Make sure the correct FPGA program was installed by
selecting the
Settings
button in the
ADC Data Capture
block in VisualAnalog. Then select the
FPGA
tab and
verify that the proper FPGA bin file is selected for the part.
If VisualAnalog indicates that the
FIFO Capture timed out
,
do the following:
•
Make sure all power and USB connections are secure.
•
Probe the DCOA signal at RN601 on the evaluation board
and confirm that a clock signal is present at the ADC
sampling rate.
Summary of Contents for AD9286-500EBZ
Page 6: ...UG 191 AD9286 500EBZ User Guide Rev A Page 6 of 24 09346 006 Figure 6 VisualAnalog Main Window...
Page 16: ...UG 191 AD9286 500EBZ User Guide Rev A Page 16 of 24 09346 020 Figure 20 Top Side...
Page 17: ...AD9286 500EBZ User Guide UG 191 Rev A Page 17 of 24 09346 021 Figure 21 Ground Plane Layer 2...
Page 18: ...UG 191 AD9286 500EBZ User Guide Rev A Page 18 of 24 09346 022 Figure 22 Power Plane Layer 3...
Page 19: ...AD9286 500EBZ User Guide UG 191 Rev A Page 19 of 24 09346 024 Figure 23 Power Plane Layer 4...
Page 20: ...UG 191 AD9286 500EBZ User Guide Rev A Page 20 of 24 09346 025 Figure 24 Ground Plane Layer 5...
Page 21: ...AD9286 500EBZ User Guide UG 191 Rev A Page 21 of 24 09346 025 Figure 25 Bottom Side...
