Analog Devices AD5934, Manual

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AD5934
Rev. A | Page 6 of 40
I
2
C SERIAL INTERFACE TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted (see Figure 2).
Table 2.
Parameter
1
Limit at T
MIN
, T
MAX
Unit Description
f
SCL
400 kHz max SCL clock frequency
t
1
2.5 μs min SCL cycle time
t
2
0.6 μs min t
HIGH
, SCL high time
t
3
1.3 μs min t
LOW
, SCL low time
t
4
0.6 μs min t
HD, STA
, start/repeated start condition hold time
t
5
100 ns min t
SU, DAT
, data setup time
t
6
2
0.9 μs max t
HD, DAT
, data hold time
0 μs min t
HD, DAT
, data hold time
t
7
0.6 μs min t
SU, STA
, setup time for repeated start
t
8
0.6 μs min t
SU, STO
, stop condition setup time
t
9
1.3 μs min t
BUF
, bus free time between a stop and a start condition
t
10
300 ns max t
R
, rise time of SDA when transmitting
0 ns min t
R
, rise time of SCL and SDA when receiving (CMOS compatible)
t
11
300 ns max t
F
, fall time of SCL and SDA when transmitting
0 ns min t
F
, fall time of SDA when receiving (CMOS compatible)
250 ns max t
F
, fall time of SDA when receiving
20 + 0.1 C
b
3
ns min t
F
, fall time of SCL and SDA when transmitting
C
b
400 pF max Capacitive load for each bus line
1
Guaranteed by design and characterization, not production tested.
2
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V
IH MIN
of the SCL signal) to bridge the undefined falling edge of SCL.
3 C
b
is the total capacitance of one bus line in pF. Note that t
R
and t
F
are measured between 0.3 VDD and 0.7 VDD.
053
25
-00
2
SCL
SDA
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
t
9
t
3
t
10
t
11
t
4
t
4
t
6
t
2
t
5
t
7
t
8
t
1
Figure 2. I
2
C Interface Timing Diagram