Anadigm AnadigmApex User Manual Download Page 6

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AN231K04-DVLP3 – AnadigmApex Development Board

UM023100-K001h

Page 6 of 16

5.0

Evaluating Multi-chip Designs – Daisy Chaining

Figure 3 shows an example of how to chain 2 boards together. More boards can be chained using the
instructions shown in this figure.

Figure 3: Positions of Jumpers and Default Settings

Summary of Contents for AnadigmApex

Page 1: ...claims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typical s...

Page 2: ...ew with this revision of Development Kit board Board footprint 4 8 x 3 8 inches Standard USB serial interface for downloading AnadigmDesigner 2 circuit files Ability to store configurations in to onbo...

Page 3: ...lopment Board UM023100 K001h Page 3 of 16 2 0 Layout Figures 2 shows the layout of the board allowing easy location of all the components power connections and jumpers Figure 2 Top level layout of the...

Page 4: ...sing a standard RS232 cable Check the position of Jumper pair J15 should be both jumpers in the upper position Open AnadigmDesigner 2 on the PC create a circuit and click on Configure If configuration...

Page 5: ...o to settings preferences and choose the Port Tab If the installation has been successful the dropdown Port select menu will allow you to select COM CP2101 USB to UARF Bridge Controller COM this numbe...

Page 6: ...0 K001h Page 6 of 16 5 0 Evaluating Multi chip Designs Daisy Chaining Figure 3 shows an example of how to chain 2 boards together More boards can be chained using the instructions shown in this figure...

Page 7: ...to put the board in EPROM mode 2 Make sure that the jumper J1 is placed to the right to enable the PIC 3 Make sure that there is no jumper on J6 FLASH storage must be enabled to write the EPROM 4 Rem...

Page 8: ...f the digital section of the development board is removed or ignored by pulling jumpers J5 the dpASP can be configured directly using any processor with an SPI interface or port configured with approp...

Page 9: ...ERRb is pulled high CS1b is tied low and CS2b is pulled low J5 Connects the digital section to the analog section All 15 jumpers should be on Fully connects power ground and all dpASP digital signals...

Page 10: ...gure 5 details two suggested Rauch filter circuits These can be easily implemented by adding appropriate components to the p c b This picture of the p c b show s an example of one of two p c b layouts...

Page 11: ...30kHz R1 R2 10k R3 5k C1 0 75nF C2 0 375nF For Fc 40kHz R1 R2 10k R3 5k C1 0 56nF C2 0 28nF For Fc 10kHz R1 R2 10k R3 5k C1 2 2nF C2 1 1nF Alternative math C1 2 C2 G 1 Q 2 R1 1 Q 4 G F C2 R2 G R1 R3...

Page 12: ...ed for components you may add to the breadboard area The current is limit by the regulator power dissipation dpASP Input Voltage Fin 0 5 3 6 V Direct input to dpASP on analog IO header pins or digital...

Page 13: ...AN231K04 the AnadigmApex Development Board UM023100 K001h Page 13 of 16...

Page 14: ...AN231K04 the AnadigmApex Development Board UM023100 K001h Page 14 of 16...

Page 15: ...AN231K04 DVLP3 AnadigmApex Development Board UM023100 K001h Page 15 of 16...

Page 16: ...AN231K04 the AnadigmApex Development Board UM023100 K001h Page 16 of 16 Notes For More information Contact http www anadigm com support anadigm com...