FIGURE E-2B. PHASE ll INTEGRATE INPUT
POLARITY
FF
3
C
STRAY
C
REF
6
1
V
IN
ZERO CROSSING
DETECTOR
COMPARATOR
_
A3
+
INTEGRATOR
_
A2
+
C
AZ
BU
F
FER
_
A1
+
1 µF
4
2
5
R
INT
C
INT
FIGURE E-2C. PHASE lll AND DE-INTEGRATE
POLARITY
FF
3
C
STRAY
C
REF
6
1
V
IN
ZERO CROSSING
DETECTOR
COMPARATOR
_
A3
+
INTEGRATOR
_
A2
+
C
AZ
BU
FFE
R
_
A1
+
1 µF
4
2
5
R
INT
C
INT
FIGURE E-2D. PHASE lll AND DE-INTEGRATE
POLARITY
FF
3
C
STRAY
C
REF
6
1
V
IN
ZERO CROSSING
DETECTOR
COMPARATOR
_
A3
+
INTEGRATOR
_
A2
+
C
AZ
BUFFER
_
A1
+
1 µF
4
2
5
R
INT
C
INT
Figures E2. Main Analog Section of DVM Circuit - IC1 and IC2
3
FIGURE E-2A. PHASE l AUTO-ZERO
6
1
V
IN
C
STRAY
C
REF
ZERO CROSSING
DETECTOR
COMPARATOR
_
A3
+
INTEGRATOR
_
A2
+
C
AZ
BUF
FER
_
A1
+
1 µF
4
2
5
R
INT
C
INT