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Chapter 1
Getting Started
If the 10 MHz clock is present on both the PXI_CLK10_IN pin of the
System Timing Slot and the 10 MHz REF IN connector on the rear of the
chassis, the signal on the System Timing Slot is selected. Refer to Table 1-2
which explains how the 10 MHz clocks are selected by the backplane.
A copy of the backplane’s PXI_CLK10 is exported to the 10 MHz REF
OUT connector on the rear of the chassis. This clock is driven by an
independent buffer. Refer to Appendix A,
, for the
specification information for the 10 MHz REF OUT signal on the rear
panel of the chassis.
PXIe_SYNC_CTRL
PXIe_SYNC100 is by default a 10 ns pulse synchronous to PXI_CLK10.
The frequency of PXIe_SYNC100 is 10/
n
MHz, where
n
is a positive
integer. The default for
n
is 1, giving PXIe_SYNC100 a 100 ns period.
However, the backplane allows
n
to be programmed to other integers. For
instance, setting
n
= 3 gives a PXIe_SYNC100 with a 300 ns period while
still maintaining its phase relationship to PXI_CLK10. The value for
n
may
be set to any positive integer from 1 to 255.
The system timing slot has a control pin for PXIe_SYNC100 called
PXIe_SYNC_CTRL for use when
n
> 1. Refer to Table B-6,
Connector Pinout for the System Timing Slot
, for system timing slot pinout.
Refer to Appendix A,
, for the PXIe_SYNC_CTRL input
specifications.
Table 1-2.
Backplane External Clock Input Truth Table
System Timing Slot
PXI_CLK10_IN
Rear Chassis Panel
10 MHz REF IN
Backplane PXI_CLK10,
PXIe_CLK100 and PXIe_SYNC100
No clock present
No clock present
Backplane generates its own clocks
No clock present
10 MHz clock present
PXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 all phase-locked to
Rear Chassis Panel—10 MHz REF IN
10 MHz clock present
No clock present
PXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 all phase-locked to
System Timing Slot—PXI_CLK10_IN
10 MHz clock present
10MHz clock present
PXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 all phase-locked to
System Timing Slot—PXI_CLK10_IN
Manual
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