Magic 485F Adapter
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MAGIC 485F
1 INTRODUCTION
1.1 General Description
The Magic 485F ‘MAGIC converter’ transfers data between RS232 & RS485 networks. The unit
is ‘magic’ in that, unlike conventional converters, it does not require the RTS signal to control
RS485 transmitter turnaround. Instead the RS485 transmitter is enabled whenever a valid start
bit is detected on the RS232 input. This feature can be very useful when connecting RS232
based modems, or other systems that do not support RTS handshaking to RS485 multidrop
networks.
The data conversion process changes only electrical levels and the pin-out configuration is in
accordance with the appropriate standards. As default the unit is supplied for the RS232 host
device configured as Data Terminal Equipment (DTE) but can be changed by jumpers to a Data
Communication Equipment (DCE).
RS485 multi-drop operation allows up to 32 devices to be connected in a simple network on a
single serial bus. The transmitter has a tri-state output and is automatically disabled to allow
reception over the same wire pair.
DC power for the Magic 485F Adapter must be applied from an external source. The DC power
lines plus the RS422/485 data and control signals are connected through a pluggable 8 way
screw terminal assembly at the free end of the Adapter.
1.2 The Products Described in this Manual
The 485F range of boards share some common circuitry and features and are referred to in this
manual either generically or individually:
485F
Refers to both boards
485F25
Refers to the 25 way D-type version only
485F9
Refers to the 9 way D-type version only
1.3 Circuit Operation
The Magic 485F Adapter converts the electrical levels of signals from those specified for RS232
to the RS422/485 levels and vice versa. This conversion is done via intermediate TTL levels.
RS232 <–––> TTL
U2 is a MAX2322E (or equivalent) 5 V powered CMOS RS232 Driver/Receiver. A DC-DC
converter is built into the chip to provide a typical ±9 V output swing of the RS232 lines.
This receiver accepts signal at RS232 levels and converts these signals to TTL levels for
internal use. The first receiver accepts the transmitted data (TxD) signal from the RS232 port
and translates it to TTL levels for onward conversion by the RS422/485 driver.
This line is then fed to a FPGA device, U4, which monitors the data coming into the unit. If
the unit detects a valid start bit, the device enables the transmitter and disables the
receiver of the MAX491 transceiver chip U1. Once the packet of data is transmitted and
the turnaround time has passed, as set by SW1, the unit reverts to receive mode.
