AMD Confidential
User Manual
November 21
st
, 2008
186
Appendix A
A.6 Instruction Reference
This section specifies the hexadecimal and/or binary encodings for the opcodes that
SimNow does (
), does not (
) or does partially (
) simulate when simulating an
AMD 8
th
Generation CPU, Rev. F.
A.6.1 Notation
A.6.1.1
Mnemonic Syntax
Each instruction has a syntax that includes the mnemonic and any operands that the
instruction can take. Figure A-1 shows an example of a syntax in which the instruction
takes two operands. In most instruction that take two operands, the first (left-most)
operand is both a source operand (the first source operand) and the destination operand.
The second (right-most) operand serves only as a source, not a destination.
Figure A-1: Syntax for Typical Two-Operand Instruction
The following notation is used to denote the size and type of source and destination
operands:
cReg
– Control Register.
dReg
– Debug register.
imm8
– Byte (8-Bit) immediate.
imm16
– Word (16-Bit) immediate.
imm16/32
– Word (16-bit) or doubleword (32-bit) immediate.
imm32
– Doubleword (32-bit) immediate.
imm32/64
– Doubleword (32-bit) or quadword (64-bit) immediate.
imm64 – Quadword (64-bit) immediate.
mem
– An operand of unspecified size in memory.
mem8
– Byte (8-bit) operand in memory.
mem16
– Word (16-bit) operand in memory.
mem16/32
– Word (16-bit) or doubleword (32-bit) operand in memory.
mem32
– Doubleword (32-bit) operand in memory.
mem32/48
– Doubleword (32-bit) or 48-bit operand in memory.
mem48
– 48-bit operand in memory.
mem64
– Quadword (64-bit) operand in memory.
mem16:16
– Two sequential word (16-bit) operands in memory.
mem16:32
– A doubleword (32-bit) operand followed by a word (16-bit) operand
in memory.
mem32real
– Single precision (32-bit) floating-point operand in memory.
Mnemonic
First Operand and
Destination Operand
Second Source Operand
ADDPD xmm1, xmm2/mem128
