AMD Elan SC520, User Manual, Page: 205 / 444

SDRAM Controller
Élan™SC520 Microcontroller User’s Manual 10-27
Figure 10-12 SDRAM Auto Refresh Cycle
10.5.7.5 SDRAM Mode Register Access Cycles
The mode register contained in the SDRAM devices is used to define the specific mode of
operation of the SDRAM. This definition includes the selection of the burst length, burst
type, CAS latency, operating mode, and write burst mode. An SDRAM Load Mode
Command is shown in Figure 10-13. See “SDRAM Device Initialization” on page 10-30 for
information on programming the mode register.
Figure 10-13 SDRAM Mode Register Access
10.5.8 Interrupts
The SDRAM controller implements Error Correction Code logic to detect and correct single-
bit errors and detect multi-bit errors.
Separate interrupts can be generated for both single-bit error and multi-bit error detection.
These two interrupts are routed from the SDRAM controller to the ÉlanSC520
microcontroller’s programmable interrupt controller (PIC).
■ These two interrupts can be individually enabled by using the MULT_INT_ENB and
SGL_INT_ENB bits in the ECC Control (ECCCTL) register (MMCR offset 20h).
■ The interrupt signals remain asserted to the PIC until a write is performed to the
MBIT_ERR and SBIT_ERR status bits in the ECC Status (ECCSTA) register (MMCR
offset 21h). This write is typically performed by the interrupt handler associated with the
interrupt.
Note: The multi-bit error interrupt, when enabled, always generates a non-maskable
interrupt (NMI).
Nop Auto Ref. Auto Ref. Auto Ref. Auto Ref.
All Bnk.
Pre.
CLKMEMOUT
SCS0
SCS1
SCS2
SCS3
MA12–MA0,
Command
BA1–BA0
Auto Ref. Load Mode Act
Code Row
CLKMEMOUT
MA12–MA0,
Command
BA1–BA0