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23614K—October 2003

AMD Athlon™ Processor Model 4 Revision Guide

Preliminary Information

1

Product Errata

This section documents AMD Athlon processor model 4 product errata. The errata are divided into
categories to assist referencing particular errata. A unique tracking number for each erratum has been
assigned within this document for user convenience in tracking the errata within specific revision
levels. Table 1 cross-references the revisions of the processor to each erratum. An “X” indicates that
the erratum applies to the stepping. The absence of an “X” indicates that the erratum does not apply
to the stepping. Shading within the table indicates an addition or modification from the previous
release of this document.

Note:

There can be missing errata numbers. Errata that have been resolved from early revisions of the
processor have been deleted, and errata that have been reconsidered may have been deleted or
renumbered.

Table 1.

Cross-Reference of Product Revision to Errata

Errata Numbers and Description

Revision Numbers

A4

A5

A6

A7

A9

5  MCA  Bus  Unit  Control  Register  MSR  408H  Returns  Incorrect  Information

X

X

X

X

X

10 Resistance Value of the ZN and ZP Pins

X

X

11 PLL Overshoot on Wake-Up from Disconnect Causes Auto-Compensation
Circuit to Fail

X

X

X

X

X

13  Instruction  Execution  Deadlock 

X

X

X

X

14 Processors with Half-Frequency Multipliers May Hang Upon Wake-up from
Disconnect 

X

X

X

X

X

15 Processor Does Not Support Reliable Microcode Patch Mechanism 

X

16 INVLPG Instruction Does Not Flush Entire Four-Megabyte Page Properly with
Certain Linear Addresses 

X

X

X

X

X

17 Code Modifications that Coincide with Level 2 Instruction TLB Translations
May Escape Detection Resulting in Stale Code Execution

X

X

X

X

X

20 A Speculative SMC Store Followed by an Actual SMC Store May Cause One-
Time Stale Execution

X

X

X

X

X

21 Real Mode RDPMC with Illegal ECX May Cause Unpredictable Operation

X

X

X

X

X

22  Using  Task  Gates  With  Breakpoints  Enabled  May  Cause  Unexpected  Faults

X

X

X

X

X

23  Single  Step  Across  I/O  SMI  Skips  One  Debug  Trap

X

X

X

X

X

24 Software Prefetches May Report A Page Fault

X

X

X

X

X

Summary of Contents for Athlon 4

Page 1: ...AMD Athlon Processor Model 4 Revision Guide Publication 23614 Rev K Issue Date October 2003 Preliminary Information...

Page 2: ...ation Except as set forth in AMD s Standard Terms and Conditions of Sale AMD assumes no liability whatsoever and disclaims any express or implied warranty relating to its products including but not li...

Page 3: ...n History Date Rev Description October 2003 K Revised erratum 24 June 2003 J Added erratum 24 December 2002 I Added errata 21 23 July 2002 H Added erratum 20 March 2002 G Added erratum 17 April 2001 F...

Page 4: ...s on page 20 shows the AMD Athlon processor model 4 identification numbers returned by the CPUID instruction for each revision of the processor Technical and Documentation Support This section which s...

Page 5: ...roduct Revision to Errata Errata Numbers and Description Revision Numbers A4 A5 A6 A7 A9 5 MCA Bus Unit Control Register MSR 408H Returns Incorrect Information X X X X X 10 Resistance Value of the ZN...

Page 6: ...the upper 32 bits in EDX Non conformance A read to the Machine Check Architecture MCA Bus Unit Control MSR 408h MC2_CTL returns incorrect information in EDX It returns the information stored in the up...

Page 7: ...t on System The AMD Athlon system bus signal quality for signals driven to the Northbridge may be adversely affected Suggested Workaround All motherboards should have ZN ZP resistors set to approximat...

Page 8: ...strength levels in the driver compensation circuit The compensation circuit attempts to correct the drive strength but if there is not sufficient time to perform this function the system bus cannot op...

Page 9: ...as specified Non conformance Under rare and unlikely conditions the load store unit instruction scheduler and effective address generation unit interact in such a way that deadlock a occurs preventin...

Page 10: ...from a low power state and reconnect to the system bus when the nominal operating frequency is generated with a half frequency multiplier This circuit is rarely observed to glitch when coming out of...

Page 11: ...properly after a microcode patch is loaded Non conformance The processor has the patch RAM BIST function disabled Since BIST is not run on the patch RAM reliable operation of the patch RAM cannot be a...

Page 12: ...ted logical address Non conformance When the logical address designated by the INVLPG instruction is mapped by a 4 Mbyte page mapping and LA 21 is equal to one it is possible that the TLB will still r...

Page 13: ...ification has generated an instruction cache invalidation 2 The processor is fetching the line that is being invalidated 3 The fetch misses in the Level 1 instruction TLB 4 The fetch hits in the Level...

Page 14: ...invalidates the instruction cache line with address A and brings the line into the L1 data cache marking it as modified However the instruction buffer which also contains some bytes from address A is...

Page 15: ...ection exception Non conformance If the RDPMC is executed in real mode with a specific illegal value of ECX 4 then the processor may incorrectly enter the GP fault handler as if it were in 32 bit real...

Page 16: ...conformance When a task gate is used by a CALL or JMP instruction and any debug breakpoint is enabled through the DR7 LE or GE bits the processor may under certain timing scenarios incorrectly use the...

Page 17: ...estart the processor should immediately enter the debug trap handler Non conformance Under this scenario the processor does not enter the debug trap handler but instead returns to the instruction foll...

Page 18: ...y occur infrequently on a prefetch instruction Suggested Workaround Two workarounds are described for this erratum Kernel Workaround The Operating System kernel can work around the erratum by allowing...

Page 19: ...ion per cache line a naturally aligned 64 byte quantity and ensuring one of the following In many cases if a particular target address of a prefetch is known to encounter this errata simply change the...

Page 20: ...n 2 Revision Determination Table 2 shows the AMD Athlon processor model 4 identification number returned by the CPUID instruction for each revision of the processor Table 2 CPUID Values for the Revisi...

Page 21: ...to the data sheets listed in this section for product marking information AMD Athlon Processor Model 4 Data Sheet order 23792 AMD 751 System Controller Data Sheet order 21910 AMD 756 Peripheral Bus C...

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