General Circuit Interface (GCI)
17-20
Am186™CC/CH/CU Microcontrollers User’s Manual
■
Monitor Channel Transmit Abort Request Received: Indicates that an abort request
has been received on the monitor channel. This indicates that the receiver on the other
end of the Monitor channel has failed to receive the transmitted data correctly and is
requesting that the current transmission be discontinued and the data transmission be
repeated through software.
■
Monitor Channel End-of-Message Received: Indicates that an EOM has been
received on the monitor channel. This indicates that the message currently being
received has concluded.
■
Monitor Channel Transmit Buffer Available: Indicates that a new byte of data can be
loaded into the Monitor Transmit Data register.
■
Monitor Channel Receive Data Available: Indicates that a byte of data has been
received on the monitor channel and is available in the Monitor Receive Data register.
17.5.9
Software-Related Considerations
To enable the GCI interface, software must set the MODE bit field to 10b in the TSA
Channel A Configuration (TSACON) register. This is necessary regardless of whether TSA
Channel A is being used.
17.5.10
Comparison to Other Devices
The Am186CC microcontroller’s GCI interface is similar to the AMD Am79C30 in clock slave
mode.
17.6
INITIALIZATION
On external and internal reset, the following occurs:
■
The TSAs default to non-GCI mode.
■
The GCI signals default to alternate functionality as shown in Table 17-1 on page 17-3.
■
The EXSYNC bit of the SYSCON register is cleared, making the HDLC Channel C
interface available for raw DCE or PCM highway operation.
■
The MODE field of the TSxCON register is cleared, specifying raw DCE operation.
■
The GCIDEN bit of the HxTCON1 register is cleared, disabling GCI D-Channel control
of the HDLC channel.
■
The MCHEN bit of the GPCON register is cleared, disabling both monitor channels.
■
The MCHSEL bit of the GPCON register is cleared, selecting monitor channel 1.
■
The ICSEL bit of the GPCON register is cleared, selecting IC channel 1.
■
The BRDIS bit of the GPCON register is cleared, enabling bus reversal.
■
The MXBA bit of the GISTAT register is set, indicating that a new byte of data can be
loaded into the GMTD register.
■
All GCI interrupts enables are cleared to 0 in the GIMSK register, masking the interrupts.
■
The TICEN and ECHOEN bits are cleared to 0 in the GTIC register, disabling TIC bus
access and D-channel echo compares, respectively.
Summary of Contents for Am186 CC
Page 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Page 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Page 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Page 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Page 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Page 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Page 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Page 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Page 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...