DRAM Controller
Am186™CC/CH/CU Microcontrollers User’s Manual
6-5
The user can re-enable UCS by clearing the UDEN bit in the UMCS register. Doing so
disables refreshing the upper bank of DRAM. If the data in the upper bank of DRAM does
not have to be retained, no special action is required. If the data in the upper bank of DRAM
must be retained, two options are available. The refresh control unit counter can be
monitored through the EDRAM register. When the counter reaches all zeros, a refresh
occurs. The user can then disable the upper bank of DRAM using the UDEN bit in the
UCMS register, access the UCS-connected device, and then re-enable the upper bank of
DRAM before the next refresh is scheduled to occur (usually 15.6 µs). This retains the data
in the upper bank of DRAM.
Alternatively, a software routine can conduct a read from all rows of the upper DRAM. Then
the UDEN bit can be switched to enable UCS and disable RAS1. The user then has the
total refresh time (usually 16 ms) before the DRAM must be re-enabled to retain its data.
After re-enabling the DRAM, the user should once again conduct reads on all the DRAM
row addresses before letting the refresh controller resume refreshing the DRAM.
6.5.4
Option to Overlap DRAM with PCS
The PCS7–PCS0 signals can overlap DRAM blocks with different wait states without
external or internal bus contention. The RAS0 or RAS1 signals assert along with the
appropriate PCS signal. The CAS0 and CAS1 signals do not assert, preventing the DRAM
from writing erroneously or driving the data bus during a read. The PCS signals must be
configured to have the same or greater number of wait states than the DRAM. In the case
of an overlap, the bus width during PCS accesses is 16 bits.
6.5.5
DRAM Refresh
6.5.5.1
DRAM Refresh Cycle
When DRAM refresh is enabled, it operates off the processor internal clock. The following
steps outline the refresh process:
1. The Refresh Control unit (RCU) checks the T bit field in the EDRAM register to see if
the counter = 0. If not, the clock decrements by 1 and the counter is checked again. This
process is repeated until the counter = 0.
2. When the refresh counter = 0, the counter reloads the value from the RC field of the
CDRAM register and starts again, simultaneously generating a CAS-before-RAS
request to the bus interface unit. The DRAM refresh process continues until the EN bit
in the EDRAM register is cleared.
3. The bus interface acknowledges the request. The refresh request stays active until the
bus becomes available.
4. When the bus is free, the bus interface runs a “dummy read” cycle. Note that the refresh
clock counter continues counting independent of when the bus interface services the
refresh request. If the HLDA signal is active when a refresh request is generated
(indicating a bus hold condition), then the microcontroller deactivates the HLDA signal
to perform a refresh cycle when the hold is negated. The circuit external bus master
must negate the HOLD signal for at least one clock to allow the refresh cycle to execute.
The refresh cycle has priority over all other bus cycles (CPU, DMA, and so on). Refresh
changes no bits and looks like a read cycle. The various cycles follow this priority ranking:
refresh (highest priority), HOLD, DMA, and CPU (lowest).
5. After the refresh cycle completes, the HLDA signal goes active and the controller
continues with whatever activity was occurring before the refresh.
6. The request is removed.
Summary of Contents for Am186 CC
Page 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Page 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Page 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Page 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Page 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Page 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Page 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Page 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Page 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...