Altera Stratix II GX PCI Express Page 29 Reference Manual Download

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Altera Corporation

Reference Manual

2–19

August 2006

Stratix II GX PCI Express Development Board

Board Components & Interfaces

For more information about the advanced parallel flash loader
settings, refer to Chapter 2 of the

Configuration Handbook,

Configuring Stratix II and Stratix II GX Devices

CONFIGn

FPGA

nCONFIG

connection

1.8-V CMOS in

STATUSn

FPGA

nSTATUS

connection

1.8-V CMOS in

FLASH_A(24:0)

Flash address bus

1.8-V CMOS out (25 bit)

FLASH_D

Flash data bus

1.8 -V CMOS in/out (16 bit)

FLASH_CEn

Flash chip enable

1.8-V CMOS out

FLASH_OEn

Flash output enable

1.8-V CMOS out

FLASH_WEn

Flash write enable

1.8-V CMOS out

CONFIG_MODE(1:0)

Configuration mode input 1.8-V CMOS in (2 bits)

MSEL(3:0)

FPGA mode select output 1.8-V CMOS out (4 bits)

MAX_EN

Enables operation for
PFL

1.8-V CMOS in

FPGA_PGM(2:0)

Remote configuration
page select

1.8-V CMOS in (3 bits)

DIPSW_PGM(2:0)

DIP switch configuration
page select

1.8-V CMOS in (3 bits)

MAXII_CLK_IN

100-MHz clock input

1.8-V CMOS in

TMS

JTAG mode select

N/A

TDI

JTAG data in

N/A

TDO

JTAG data out

N/A

TCK

JTAG clock

N/A

VCCIO1

I/O bank 1 power

1.8 V

VCCIO2

I/O bank 2 power

1.8 V

VCCINT

Core power

1.8 V

GNDIO

I/O GND

GND

GNDINT

Core GND

GND

Table 2–10. MAX II CPLD Signals & I/O Requirements (Part 2 of 2)

Signal Name

Description

Signal Type

Summary of Contents for Stratix II GX PCI Express

Page 1: ...101 Innovation Drive San Jose CA 95134 408 544 7000 www altera com Stratix II GX PCI Express Development Board Reference Manual Document Version 1 0 1 Document Date April 2007 ...

Page 2: ...warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the ap plication or use of any information product or service described herein except as expressly agreed to in writing b...

Page 3: ...figuration File Storage 2 17 MAX II CPLD Configuration Controller 2 18 Status and Channel Activity LEDs 2 21 General User Interfaces 2 22 Push Button Switches S1 Through S4 2 22 User Defined DIP Switch S5 2 23 User LEDs D9 Through D16 2 23 Configuration DIP Switch 2 24 Board Specific LEDs 2 25 FPGA Transceiver Channel Activity LEDs 2 25 Power Configuration and Traffic Activity LEDs 2 26 Standard C...

Page 4: ...ndbook Volume 1 Temperature Sensor 2 54 Heat Sink and Fan 2 55 Power Supply 2 55 Power Supply for Each Component 2 55 Components Attached to Each Power Rail 2 56 Power Distribution System 2 58 Termination 2 60 DDR2 Memory 2 60 QDRII Memory 2 60 PCI Express 2 60 ...

Page 5: ...products consult the sources shown below Chapter Date Version Changes Made All August 2006 1 0 0 First publication All April 2007 1 0 1 Added warning not to use external power supply when the Altera Stratix II GX PCI Express development board is powered from the host computer chassis Information Type USA Canada All Other Locations Technical support www altera com mysupport www altera com mysupport...

Page 6: ...in a document and titles of on line help topics are shown in quotation marks Example Typographic Conventions Courier type Signal and port names are shown in lowercase Courier type Examples data1 tdi input Active low signals are denoted by suffix n e g resetn Anything that must be typed exactly as it appears is shown in Courier type For example c qdesigns tutorial chiptrip gdf Also sections of an a...

Page 7: ...ors you can enable the inter operability of the Stratix II GX embedded transceivers with third party application specific standard products ASSPs in either point to point or switching and bridging applications Because the Stratix II GX embedded transceivers can implement the entire PCIe interface on one device the Stratix II GX PCI Express development board offers a high bandwidth low latency powe...

Page 8: ...ource either PCIe motherboard Laptop style DC power supply via DC input jack Communication ports PCIe edge connector High speed Mezzanine cards Gigabit Ethernet SFP modules Joint Test Action Group JTAG header Clocking circuitry Three high speed clock oscillators to support Stratix II GX transceivers and user logic 100 MHz 155 52 MHz 156 25 MHz SMA connector for external clock input and output Bloc...

Page 9: ...ed Therefore use anti static handling precaution when touching the board 155 52 MHz 72 MB QDRII x36 1 8V HSTL 88E1111 GigE PHY RJ45 1 8V HSTL TX RX LEDs User LEDs 1 8V 2 5V CMOS 156 250 MHz 100 000 MHz 512 MB Flash MAX II Device HMC Port A Stratix II GX Device HMC Port B x8 PCIe Edge Connector SFP A SFP B 1 8 V CMOS 6x XCVR CMOS LVDS 4x XCVR 1 CMOS LVDS 1x XCVR 1x XCVR 8x XCVR REFCLK 256 MB DDR2 S...

Page 10: ...1 4 Reference Manual Altera Corporation Stratix II GX PCI Express Development Board August 2006 Handling the Board ...

Page 11: ...and is divided into the following major blocks Featured device Clocking circuitry Configuration User interface components Standard communication ports Off chip memory Power supply Termination 1 Board schematics the physical layout database and manufacturing files for the Stratix II GX PCI Express PCIe development board are included in the PCI Express Development Kit Stratix II GX Edition in the fo...

Page 12: ...Flash Device U3 User LEDs D9 through D16 MAX II Device U4 High Speed Mezzanine Card Interfaces A B J1 and J2 User Push Button Switches S1 S4 DDR2 32 x 16 Mbytes SDRAM U5 U8 U11 U13 Transmit Receive Yellow LEDs D5 and D6 DDR2 64 x 8 Mbytes SDRAM U2 Temperature Sensor With Alarm U7 100 MHz Crystal X1 155 25 MHz Crystal X4 PCI Express x8 Edge Connector QDRII SRAM U6 SFP Ports A and B J6 J7 JTAG Heade...

Page 13: ...l 2 3 August 2006 Stratix II GX PCI Express Development Board Board Components Interfaces Figure 2 2 shows a diagonal view of the Stratix II GX PCIe development board Figure 2 2 Diagonal View of the Stratix II GX PCIe Development Board ...

Page 14: ...t controls the FPGA configuration settings 2 23 Status LEDs D1 D2 D8 D19 D22 LEDs that display power and configuration status 2 25 Channel activity LEDs D3 D6 D17 D18 D23 D29 LEDs that display RX and TX transceiver channel activity 2 24 User I O Push button switches S1 S4 User defined push button switches 2 21 User LEDs D9 D16 User defined LEDs 2 23 8 pin DIP switch S5 User defined DIP switches 2 ...

Page 15: ...Power switch SW1 Switches the board s power on or off 2 55 Table 2 1 Stratix II GX PCIe Development Board Features Component Interface Board Reference Description Page Table 2 2 Stratix II GX Features Architectural Feature Results The Altera third generation FPGA with embedded transceivers Provides a robust design solution for the most popular high speed serial interfaces Provides optimum jitter p...

Page 16: ...logic elements LEs 8 phase locked loops PLLs 650 user I O 4 520 448 RAM bits 192 18x18 multipliers The larger EP2SGX130GF1508 Stratix II GX device provides the following 20 transceiver channels 78 source synchronous channels 132 540 LEs 8 PLLs 798 user I O 6 747 840 RAM bits 252 18x18 multipliers I O Clocking Resources This section lists specific I O and clocking resources available on both the EP...

Page 17: ...vice I O Bank Resources Figure 2 4 illustrates the available I O mapping on both the EP2SGX90FF1508 and the EP2SGX130GF1508 devices B4 B9 6 B11 6 B3 B7 B8 95 I O 100 I O 104 106 94 I O 102 I O 104 4 XCVRs 124 I O 140 120 I O 156 4 XCVRs 4 XCVRs 4 XCVRs 4 XCVRs 2SGX130 only 108 B2 B1 B13 6 B10 6 B12 B14 B15 B16 B17 Note Figure is package top referenced ...

Page 18: ...ey relate to specific clock pin names noted in both the Quartus II Development Software Handbook and the Stratix II GX Device Handbook B4 B9 6 B11 6 B3 B7 B8 1 8 V 1 8 V DDR2 SSTL 18 Flash CMOS DDR2 SSTL 18 Flash CMOS QDRII HSTL 18 Flash CMOS GigE PHY CMOS QDRII HSTL Flash CMOS 1 8V SFP Port A SFP Port B HSMC Port A 2 5 V HSMC Port A LVDS CMOS 2 5 V HSMC Port B LVDS CMOS HSMC Port B PCIe Edge Lane...

Page 19: ... PLL5 PLL11 B3 B7 B8 REFCLK0 sfp_refclk xaui_refclk pcie_refclk B2 B1 B13 B14 B15 B16 B17 PLL7 PLL8 PLL1 PLL2 PLL6 PLL12 CLK12 clk1_p CLK13 CLK14 CLK15 CLK6 ddr2_sync_clk CLK7 CLK4 CLK5 REFCLK1 REFCLK0 REFCLK1 REFCLK0 REFCLK1 REFCLK0 REFCLK1 REFCLK0 REFCLK1 CLK0 FPLL7_CLK hsma_clk1 hsmcb_clk2 hsmca_clk2 hsmca_clk0 hsmb_clk1 hsmb_clk0 FPLL8_CLK CLK1 CLK2 CLK3 100m_refclk clk2_p ...

Page 20: ...zanine card port A XCVRs LVDS CMOS 1 2 V 1 5 V PCML 6 XCVR channels 1 CMOS in 1 CMOS out 2 LVDS in 2 LVDS out 2 5 V CMOS 2 5 V LVDS 84 High speed mezzanine card port B XCVRs LVDS CMOS 1 2 V 1 5 V PCML 4 XCVR channels 1 1 CMOS in 1 CMOS out 2 LVDS in 2 LVDS out 2 5 V CMOS 2 5 V LVDS 84 Gigabit Ethernet GigE physical PHY layer 12 bit 125 MHz Gigabit medium independent interface GMII 2 5 V CMOS 30 1 ...

Page 21: ...iven from the 100 MHz oscillator or from the SMA clock input for custom frequencies Pin 10 on the board configuration DIP switch controls what clock feeds the buffer see Configuration DIP Switch S6 on page 2 23 Figure 2 6 Oscillator Clocking Diagram Table 2 4 lists the board s clock distribution system 152 520 MHz SMT OSC 156 250 MHz SMT OSC 100 MHz SMT OSC MAX II Configuration Controller 88e1111 ...

Page 22: ...ownload a design file to the Stratix II GX device use the Quartus II Programmer tool f For information on the Quartus II Programmer refer to Quartus II Development Software Handbook The board s JTAG chain is connected to the Stratix II GX device the MAX II CPLD and optionally the HSMC A and B expansion connectors To configure the Stratix II GX device you need to Set up a new JTAG chain including b...

Page 23: ... JTAG Header JTAG_TDI HSMA_JTAG_TDO HSMA_JTAG_TDO DIP Switch HSMC B 1 8 V 3 3 V 1 8 V MAX II CPLD MAXII_JTAG_TDO FPGA 3 3 V 3 3 V DIP Switch S2GX_JTAG_TDO Table 2 5 JTAG Chain I O Signals Signal Name Description Signal Type JTAG_TCK JTAG clock USB Blaster output 1 8 V CMOS JTAG_TMS JTAG mode select USB Blaster output 1 8 V CMOS JTAG_TRST JTAG reset USB Blaster output 1 8 V CMOS JTAG_TDI Data outpu...

Page 24: ...ion from the flash device into the Stratix II GX device in the FPP mode The MAX II CPLD holds the configuration state machine and the flash memory holds the non volatile configuration bit streams Figure 2 8 shows the FPP configuration scheme Figure 2 8 FPP Configuration Scheme FPGA_nSTATUS FPGA_nCONFIG FPGA_CONF_DONE FPGA_PGM 2 0 FPGA_DATA 7 0 FPGA_DCLK FLASH_A 24 0 FLASH_D 15 0 FLASH_CEn FLASH_OE...

Page 25: ...ll as some JTAG chain options Refer to the General User Interfaces on page 2 21 for more information on the DIP switch Table 2 6 Configuration File Sizes Device Configuration File Size Mb 1 Compressed File Size Mb 2 EP2SGX90 25 699 104 9 251 677 EP2SGX130 37 325 760 13 437 273 Notes to Table 2 6 1 This is a preliminary value based on both the EP2SGX90 and EP2SGX130 devices 2 This value assumes ave...

Page 26: ...m into a single image to be written to flash memory using the Quartus II Programmer and a USB Blaster cable This is done via the JTAG header and the MAX II CPLD to flash memory Table 2 8 lists an example flash memory map The sizes of various blocks may change based on the settings used such as the compression setting in the Quartus II Programmer The PFL Option Bits are used by the MAX II CPLD desi...

Page 27: ...vice be ready to enter the link training state within 80 ms of the end of a fundamental reset release of the PERSTn pin This can be a power on reset where the PWR GOOD signal is FPGA Design 2 0x00BF FFFF 0x0080 0000 FPGA Design 1 0x007F FFFF 0x0040 0000 FPGA Design 0 default 0x003F FFFF 0x0000 0000 Table 2 9 Flash Interface I O Signal Name Description Signal Type FLASH_A 24 0 Address bus 1 8 V CMO...

Page 28: ...LPs and DLLps The second set of rules addresses requirements placed on the system To allow components to perform internal initialization system software must wait for at least 100 ms from the end of a reset of one or more devices before it is permitted to issue Configuration Requests to those devices A system must guarantee that all components intended to be software visible at boot time are ready...

Page 29: ...LASH_OEn Flash output enable 1 8 V CMOS out FLASH_WEn Flash write enable 1 8 V CMOS out CONFIG_MODE 1 0 Configuration mode input 1 8 V CMOS in 2 bits MSEL 3 0 FPGA mode select output 1 8 V CMOS out 4 bits MAX_EN Enables operation for PFL 1 8 V CMOS in FPGA_PGM 2 0 Remote configuration page select 1 8 V CMOS in 3 bits DIPSW_PGM 2 0 DIP switch configuration page select 1 8 V CMOS in 3 bits MAXII_CLK...

Page 30: ... list board status and channel activity LEDs Table 2 11 Status LEDs Board Reference Number Indicates D1 HSMC A detected D2 HSMC B detected D8 Successful configuration D19 Power on D20 Gigabit Ethernet 10 Mb link D21 Gigabit Ethernet 100 Mb link D22 Gigabit Ethernet 1000 Mb link Table 2 12 Channel Activity LEDs Board Reference Number Indicates D3 HSMC A TX D4 HSMC A RX D5 HSMC B TX D6 HSMC B RX D17...

Page 31: ...nd reprogram of the FPGA s design The other push buttons connect directly to user I O pins for user programming Although the RESET push button s purpose is programming its special label is intended to encourage its use as a logic reset signal for FPGA designs so that user designs are reset in a consistent manner Table 2 13 lists the schematic signal names and corresponding Stratix II GX pin number...

Page 32: ...position and each pin can be set to logic 0 by pushing it to the closed position Table 2 14 lists the DIP switch settings schematic signal name and corresponding Stratix II GX device s pin number Figure 2 9 shows the user defined DIP switch board image Figure 2 9 User Defined DIP Switch Board Image Table 2 14 User Defined DIP Switch Pin Out S5 S5 Switch Schematic Signal Name Stratix II GX Device P...

Page 33: ...umber Configuration DIP Switch S6 The configuration DIP switch is used to set up specific board functions such as FPGA bootstrap settings JTAG chain bypassing or configuration setup In the open position the selected signal is driven to logic 0 In the closed position the selected signal is driven to a logic 1 Table 2 15 User Defined LED Pin Out Board Reference Schematic Signal Name Stratix II GX De...

Page 34: ... the channels needing TX and RX LEDs Table 2 16 Configuration DIP Switch S6 Signal Names and Descriptions Schematic Signal Name Description CONFIG_MODE0 Configuration mode bit 0 CONFIG_MODE1 Configuration mode bit 1 DIPSW_PGM0 Configuration file page select bit 0 DIPSW_PGM1 Configuration file page select bit 1 DIPSW_PGM2 Configuration file page select bit 2 VCCHTX_ADJ Transceiver power select on 1...

Page 35: ...in this section PCIe edge connector interface Gigabit Ethernet interface SFP module interface High speed Mezzazine card interfaces A and B JTAG interface PCI Express Edge Connector Interface J9 The board features a x8 PCIe edge connector The high speed PCIe signals are directly routed to two Stratix II GX device transceivers quads The PCIe signals have 100 differential traces terminated on the rec...

Page 36: ...chematic Signal Name Stratix II GX Pin Number pcie_led_x1 AU11 pcie_led_x4 AG16 pcie_led_x8 AM13 pcie_perstn AL16 pcie_refclk_n AB8 pcie_refclk_p AB7 pcie_rx_n 0 AG2 pcie_rx_n 1 AE2 pcie_rx_n 2 AJ2 pcie_rx_n 3 AL2 pcie_rx_n 4 W2 pcie_rx_n 5 U2 pcie_rx_n 6 AA2 pcie_rx_n 7 AC2 pcie_rx_p 0 AG1 pcie_rx_p 1 AE1 pcie_rx_p 2 AJ1 pcie_rx_p 3 AL1 pcie_rx_p 4 W1 pcie_rx_p 5 U1 pcie_rx_p 6 AA1 pcie_rx_p 7 AC...

Page 37: ... outside of a host board where all power is derived from an external DC input jack The REFCLKp and REFCLKn signals are the 100 MHz 300 PPM differential reference clock that is driven from a base board onto the PCIe add in card This is used as the reference clock for the FPGA transceivers connected to the HSIO data channels The nominal swing for each single ended signal of the differential pair is ...

Page 38: ... with an RJ 45 jack and a dedicated 10 100 1000 base T auto negotiating Ethernet physical device The media access controller MAC layer must be implemented in the FPGA and connect to the PHY device through either the Gigabit medium independent interface GMII or medium independent interface MII Figure 2 11 shows the interface between the Stratix II GX device s MAC and the GigE PHY layer VOH 0 525V C...

Page 39: ...MAC PHY Users Guide VHDL Stratix II GX Handbook Table 2 20 lists the RJ 45 jack board reference and description Table 2 21 lists manufacturing information GTX_CLK TX_ER TX_EN TXD 7 0 GTX_CLK Stratix II GX MAC Block Marvell 88E1111 GigE PHY Layer TX_ER TX_EN TXD 7 0 RX_CLK RX_ER RX_DV RX_CLK RX_ER RX_DV RXD 7 0 CRS COL RXD 7 0 CRS COL GMII Interface Table 2 20 Component Reference RJ 45 Jack Board R...

Page 40: ...rer Manufacturer Part Number Manufacturer Website U1 10 100 1000 GigE PHY Marvel Electronics 88E1111 www marvell com Table 2 23 GigE PHY Pin Out Part 1 of 2 Schematic Signal Name Stratix II GX Device Pin Number enet_col C26 enet_crs D31 enet_gtx_clk B33 enet_intn A29 enet_mdc A28 enet_mdio E34 enet_resetn H31 enet_rx_clk M27 enet_rx_dv E28 enet_rx_er G24 enet_rxd 0 G28 enet_rxd 1 A35 enet_rxd 2 D2...

Page 41: ... board can use either the GMII or RGMII interface However because of it s simpler timing model the GMII interface is preferred enet_txd 3 C29 enet_txd 4 D26 enet_txd 5 J30 enet_txd 6 F26 enet_txd 7 F21 Table 2 24 GMII to MII I O Mapping Note 1 Marvel Target Device Pins GMII Interface Standard MII Interface Standard GTX_CLK GTX_CLK TX_CLK TX_CLK TX_ER TX_ER TX_ER TX_EN TX_EN TX_EN TXD 7 0 TXD 7 0 T...

Page 42: ...igure 2 12 Marvell 88E1111 GMII TX Timing Diagram The board provides an internal MAC core as an application layer interface for user designs You can test it by accessing the stack provided as an Altera SOPC Builder component An IP core is also available from the Altera Megafunctions Partner Program AMPPSM partner MorethanIP The MorethanIP core has been used and tested on an existing Altera daughte...

Page 43: ...requires signals only up to 5 0 Gb s but standard modules available today are typically 2 488 Gb s synchronous optical net SONET mode or below The board is designed to deliver electrical transceiver signals up to 5 0 Gb s to each SFP connector The two channels of transceivers dedicated from the FPGA come from the same transceiver block as two of the channels that are routed to the HSMC A transceiv...

Page 44: ... II GX Pin Number sfp_refclk_cn P8 sfp_refclk_cp P7 sfpa_led_rx L16 sfpa_led_tx K15 sfpa_los H16 sfpa_mod0_prsntn D11 sfpa_mod1_scl N15 sfpa_mod2_sda G11 sfpa_ratesel J21 sfpa_rx_n0 N2 sfpa_rx_p0 N1 sfpa_tx_n0 N5 sfpa_tx_p0 N4 sfpa_txdisable F10 sfpa_txfault C9 sfpb_led_rx L15 sfpb_led_tx H18 sfpb_los M16 sfpb_mod0_prsntn P18 sfpb_mod1_scl N18 sfpb_mod2_sda N17 sfpb_ratesel K18 sfpb_rx_n0 R2 sfpb_...

Page 45: ...vers Two are used by the SFP connectors and eight are used by the PCIe edge connector which leaves only six for the HSMC connectors Therefore HSMC A has only four transceivers routed to it and HSMC B has only two transceivers routed to it This is the only deviation from the HSMC specification made on these connectors Table 2 26 lists the HSMC A and B connector component reference and manufacturing...

Page 46: ...6 L39 hsma_rx_d_n 11 122 R36 hsma_rx_d_n 12 128 M38 hsma_rx_d_n 13 134 P39 hsma_rx_d_n 14 140 T34 hsma_rx_d_n 15 146 R38 hsma_rx_d_n 16 152 T39 hsma_rx_d_n 2 62 L36 hsma_rx_d_n 3 68 M36 hsma_rx_d_n 4 74 N37 hsma_rx_d_n 5 80 P36 hsma_rx_d_n 6 86 R34 hsma_rx_d_n 7 92 T37 hsma_rx_d_n 8 104 U36 hsma_rx_d_n 9 110 N35 hsma_rx_d_p 0 48 J39 hsma_rx_d_p 1 54 K38 hsma_rx_d_p 10 114 K39 hsma_rx_d_p 11 120 R3...

Page 47: ...8 A4 hsma_rx_n 2 24 E2 hsma_rx_n 3 20 G2 hsma_rx_n 4 16 J2 hsma_rx_n 5 12 L2 hsma_rx_p 0 30 C1 hsma_rx_p 1 26 A3 hsma_rx_p 2 22 E1 hsma_rx_p 3 18 G1 hsma_rx_p 4 14 J1 hsma_rx_p 5 10 L1 hsma_scl 34 H36 hsma_sda 33 F38 hsma_tx_d_n 0 49 G32 hsma_tx_d_n 1 55 J31 hsma_tx_d_n 10 115 L33 hsma_tx_d_n 11 121 R27 hsma_tx_d_n 12 127 N33 hsma_tx_d_n 13 133 P33 hsma_tx_d_n 14 139 R32 hsma_tx_d_n 15 145 T32 hsm...

Page 48: ...5 N34 hsma_tx_d_p 13 131 P34 hsma_tx_d_p 14 137 R33 hsma_tx_d_p 15 143 T33 hsma_tx_d_p 16 149 U34 hsma_tx_d_p 2 59 K32 hsma_tx_d_p 3 65 K30 hsma_tx_d_p 4 71 M32 hsma_tx_d_p 5 77 N32 hsma_tx_d_p 6 83 P30 hsma_tx_d_p 7 89 R30 hsma_tx_d_p 8 101 N27 hsma_tx_d_p 9 107 K34 hsma_tx_n 0 31 C5 hsma_tx_n 1 27 A7 hsma_tx_n 2 23 E5 hsma_tx_n 3 19 G5 hsma_tx_n 4 15 J5 hsma_tx_n 5 11 L5 hsma_tx_p 0 29 C4 hsma_t...

Page 49: ...96 W39 hsmb_clk_in_p2 156 AU39 hsmb_clk_in0 40 W37 hsmb_clk_out_n1 97 AM33 hsmb_clk_out_n2 157 AE31 hsmb_clk_out_p1 95 AM34 hsmb_clk_out_p2 155 AE32 hsmb_clk_out0 39 AN22 hsmb_d 0 41 AR22 hsmb_d 1 42 AT22 hsmb_d 2 43 AT21 hsmb_d 3 44 AP22 hsmb_led_rx N A AF25 hsmb_led_tx N A AV33 hsmb_rx_d_n 0 50 _AE36 hsmb_rx_d_n 1 56 AE38 hsmb_rx_d_n 10 116 AG35 hsmb_rx_d_n 11 122 AH36 hsmb_rx_d_n 12 128 AJ36 hs...

Page 50: ...H37 hsmb_rx_d_p 12 126 AJ37 hsmb_rx_d_p 13 132 AK36 hsmb_rx_d_p 14 138 AL39 hsmb_rx_d_p 15 144 AP39 hsmb_rx_d_p 16 150 AR39 hsmb_rx_d_p 2 60 AF39 hsmb_rx_d_p 3 66 AG38 hsmb_rx_d_p 4 72 AH39 hsmb_rx_d_p 5 78 AJ39 hsmb_rx_d_p 6 84 AK38 hsmb_rx_d_p 7 90 AN39 hsmb_rx_d_p 8 102 AE35 hsmb_rx_d_p 9 108 AF37 hsmb_rx_n 0 32 AR2 hsmb_rx_n 1 28 AN2 hsmb_rx_n 2 24 AU2 hsmb_rx_n 3 20 AW4 hsmb_rx_p 0 30 AR1 hsm...

Page 51: ...n 3 67 AE33 hsmb_tx_d_n 4 73 AB29 hsmb_tx_d_n 5 79 AC25 hsmb_tx_d_n 6 85 AD25 hsmb_tx_d_n 7 91 AE26 hsmb_tx_d_n 8 103 Y33 hsmb_tx_d_n 9 109 AA31 hsmb_tx_d_p 0 47 AA33 hsmb_tx_d_p 1 53 Y27 hsmb_tx_d_p 10 113 AB32 hsmb_tx_d_p 11 119 AC34 hsmb_tx_d_p 12 125 AD32 hsmb_tx_d_p 13 131 AC30 hsmb_tx_d_p 14 137 AB26 hsmb_tx_d_p 15 143 AD27 hsmb_tx_d_p 16 149 Y25 hsmb_tx_d_p 2 59 AA27 hsmb_tx_d_p 3 65 AD33 h...

Page 52: ...apter right angle and the top right is an ATCA mezzanine card AMC adapter The lower two figures are Altera daughter card PROTO1 adapters which are typically 3 wide and can be any length upward hsmb_tx_d_p 8 101 Y34 hsmb_tx_d_p 9 107 AA32 hsmb_tx_n 0 31 AR5 hsmb_tx_n 1 27 AN5 hsmb_tx_n 2 23 AU5 hsmb_tx_n 3 19 AW7 hsmb_tx_p 0 29 AR4 hsmb_tx_p 1 25 AN4 hsmb_tx_p 2 21 AU4 hsmb_tx_p 3 17 AW6 Table 2 28...

Page 53: ... programming as well as communication to a standard computer using a USB Blaster download cable Speeds of approximately 1 Mb s are achievable using an SOPC Builder based Nios II system in the FPGA via the Quartus II software SLDHUB primitive and the default USB Blaster driver that Quartus II software installs for JTAG programming and SignalTap debugging f For more information on the JTAG chain ref...

Page 54: ...Gb s The DDR interface signals have a single 56 Ω termination Resistors tied to a termination voltage of 0 9 V are called VTT This termination scheme is referred to as Class I termination The DDR2 components also provide an optional on chip termination of 50 75 or 150 Ω Table 2 29 lists DDR2 SRAM component reference and manufacturing information Table 2 30 lists DDR2 SRAM pin out as well as corres...

Page 55: ...5 ddr2_ba 0 AN28 ddr2_ba 1 AG24 ddr2_ba 2 AH27 ddr2_casn AG23 ddr2_ck_n 0 AV19 ddr2_ck_n 1 AT20 ddr2_ck_n 2 AN20 ddr2_ck_p 0 AW19 ddr2_ck_p 1 AU20 ddr2_ck_p 2 AP20 ddr2_cke AF18 ddr2_csn AJ25 ddr2_dm 0 AT11 ddr2_dm 1 AP12 ddr2_dm 2 AU15 ddr2_dm 3 AT17 ddr2_dm 4 AP18 ddr2_dm 5 AU24 ddr2_dm 6 AV27 ddr2_dm 7 AV30 ddr2_dm 8 AW36 ddr2_dq 0 AU9 ddr2_dq 1 AN10 ddr2_dq 10 AR12 Table 2 30 DDR2 SRAM Pin Out...

Page 56: ...dr2_dq 21 AR15 ddr2_dq 22 AW14 ddr2_dq 23 AW15 ddr2_dq 24 AN16 ddr2_dq 25 AN15 ddr2_dq 26 AU16 ddr2_dq 27 AT16 ddr2_dq 28 AN17 ddr2_dq 29 AW16 ddr2_dq 3 AW9 ddr2_dq 30 AV16 ddr2_dq 31 AP17 ddr2_dq 32 AW18 ddr2_dq 33 AT18 ddr2_dq 34 AW17 ddr2_dq 35 AR18 ddr2_dq 36 AN18 ddr2_dq 37 AT19 ddr2_dq 38 AU19 ddr2_dq 39 AN19 ddr2_dq 4 AV10 ddr2_dq 40 AP23 ddr2_dq 41 AW23 ddr2_dq 42 AW24 ddr2_dq 43 AV24 Tabl...

Page 57: ... AU27 ddr2_dq 53 AW27 ddr2_dq 54 AW28 ddr2_dq 55 AT27 ddr2_dq 56 AT28 ddr2_dq 57 AW29 ddr2_dq 58 AR28 ddr2_dq 59 AT29 ddr2_dq 6 AN11 ddr2_dq 60 AU30 ddr2_dq 61 AW30 ddr2_dq 62 AW31 ddr2_dq 63 AU31 ddr2_dq 64 AW32 ddr2_dq 65 AU32 ddr2_dq 66 AU33 ddr2_dq 67 AW34 ddr2_dq 68 AW35 ddr2_dq 69 AV34 ddr2_dq 7 AW10 ddr2_dq 70 AV37 ddr2_dq 71 AW37 ddr2_dq 8 AT12 ddr2_dq 9 AW11 ddr2_dqs 0 AT9 Table 2 30 DDR2...

Page 58: ...B s x 36 pins The bandwidth doubles to over 42 Gb s when combined read and write bandwidths are considered The QDRII interface signals do not have board level termination resistors Instead the QDRII interface is terminated using the 50 Ωoutput impedance settings available on both the Stratix II GX device and the QDRII SRAM device This approach simplifies board routing and lowers power consumption ...

Page 59: ...evice Description Manufacturer Manufacturer Part Number Manufacturer Website U6 Burst of four 300 MHz QDRII SRAM NEC UPD44165364AF5 E33 EQ2 A www nec com Table 2 32 QDRII SRAM Pin Out Part 1 of 4 Schematic Signal Name Stratix II GX Pin Number qdrii_a 0 D10 qdrii_a 1 D9 qdrii_a 10 F16 qdrii_a 11 J15 qdrii_a 12 M14 qdrii_a 13 P16 qdrii_a 14 J16 qdrii_a 15 C11 qdrii_a 16 G10 qdrii_a 17 C19 qdrii_a 18...

Page 60: ...d 15 N25 qdrii_d 16 N26 qdrii_d 17 B27 qdrii_d 18 H27 qdrii_d 19 H28 qdrii_d 2 G25 qdrii_d 20 A33 qdrii_d 21 G31 qdrii_d 22 A32 qdrii_d 23 A30 qdrii_d 24 B30 qdrii_d 25 D28 qdrii_d 26 B28 qdrii_d 27 K27 qdrii_d 28 M28 qdrii_d 29 F30 qdrii_d 3 C22 qdrii_d 30 A31 qdrii_d 31 C30 qdrii_d 32 A36 qdrii_d 33 B36 qdrii_d 34 B37 qdrii_d 35 F27 qdrii_d 4 C23 qdrii_d 5 D24 Table 2 32 QDRII SRAM Pin Out Part ...

Page 61: ...i_q 11 F13 qdrii_q 12 A11 qdrii_q 13 B12 qdrii_q 14 C13 qdrii_q 15 A13 qdrii_q 16 D14 qdrii_q 17 G15 qdrii_q 18 D19 qdrii_q 19 C18 qdrii_q 2 F14 qdrii_q 20 C17 qdrii_q 21 E15 qdrii_q 22 A18 qdrii_q 23 A17 qdrii_q 24 C16 qdrii_q 25 A16 qdrii_q 26 F15 qdrii_q 27 D17 qdrii_q 28 D18 qdrii_q 29 E18 qdrii_q 3 E12 qdrii_q 30 F17 qdrii_q 31 D15 qdrii_q 32 G16 qdrii_q 33 G17 Table 2 32 QDRII SRAM Pin Out P...

Page 62: ...n controller f For more information about the flash configuration operation refer to Configuration Schemes and Status LEDs on page 2 12 Table 2 33 lists flash memory component reference and manufacturing information qdrii_q 34 B16 qdrii_q 35 G18 qdrii_q 4 D12 qdrii_q 5 A12 qdrii_q 6 B13 qdrii_q 7 C14 qdrii_q 8 A14 qdrii_q 9 G14 qdrii_rdn N14 qdrii_rpsn F19 qdrii_rup N13 qdrii_wpsn M15 Table 2 32 Q...

Page 63: ...h_a 0 AG15 flash_a 1 AM21 flash_a 10 AG18 flash_a 11 AF21 flash_a 12 AL18 flash_a 13 AG25 flash_a 14 AV15 flash_a 15 AP27 flash_a 16 AH26 flash_a 17 AK16 flash_a 18 AN27 flash_a 19 AG26 flash_a 2 AU21 flash_a 20 AM16 flash_a 21 AK24 flash_a 22 AM27 flash_a 23 AG22 flash_a 24 AN29 flash_a 3 AU14 flash_a 4 AJ15 flash_a 5 AV12 flash_a 6 AU25 flash_a 7 AK15 flash_a 8 AL25 flash_a 9 AT23 flash_byten H2...

Page 64: ...X1619 device setting Heat Sink and Fan One of several available fans that fits the 55 mm spaced holes is the Dynatron SCP1 heat sink with an integrated fan which is used for FPGA heat dissipation on each Stratix II GX device The fan uses 190 mA at 12 V and can dissipate 25 W of heat with no additional air flow in a lab bench type environment The 12 V is delivered through a two pin 100 mil header p...

Page 65: ...ications per component Table 2 35 Power By Component Part 1 of 2 Board Device Interface Name Voltage EP2SGX90 FPGA DDR2 I O 1 8 V QDRII I O 1 8 V HSMC A LVDS 2 5 V HSMC B LVDS 2 5 V VCCPD 3 3 V VCCT XCVR TX 1 1 2 V VCCG XCVR TX buffer 1 1 5 V VCCR XCVR RX 1 1 2 V VCCA XCVR analog 1 3 3 V VCCP XCVR PCS 1 1 2 V VCCA PLL 1 2 V VCCINT 1 2 V MT47H32M16 DDR VDD 333 MHz 1 8 V VDDQ 333 MHz x72 1 8 V UPD44...

Page 66: ...ling fan 12 V HSMC A 12 V to card 12 V 3 3 V to card 3 3 V HSMC B 12 V to card 12 V 3 3 V to card 3 3 V Note to Table 2 35 1 Using pre release EPS2GX device power calculator Assumes x8 PCIe Dual 6 25Gb s mezzanine cards 1 x 6 and 1 x 4 and two SONET SFPs 20 channel EP2SGX130 device Table 2 36 Power by Rail Part 1 of 2 Power Rail Interface Name 1 2 V FPGA VCCINT FPGA VCCA PLL FPGA VCCT XCVR TX FPGA...

Page 67: ... LVDS FPGA HSMC B LVDS GigE PHY VDDO H X GigE PHY AVDD Total 3 3 V FPGA VCCPD Oscillator Marvel GigE ref Oscillator PCIe ref Oscillator XAUI ref Oscillator SONET ref Clock driver LVDS buffer 3 3 V to SFP module 3 3 V to SFP module 3 3 V to HMC A 3 3 V to HMC B Linear regulator inputs Total 5 0 V FPGA VCCA XCVR Analog Linear regulator inputs Total 12 V 12 V to card 12 V to card Cooling fan Switchin...

Page 68: ... board is connected to a computer using a PCIe x8 slot An external power supply and cables have been provided so that you can use the development board without connecting it to a PCIe chassis WARNING DO NOT CONNECT THE EXTERNAL POWER SUPPLY TO THE PCIe BOARD IF IT IS BEING POWERED FROM A BACKPLANE PCIe x8 SLOT To use the external power supply connect the power cable to the board and plug the other...

Page 69: ...atix II GX VCCio DDR2 SDRAM QDRII SRAM MAXII and FLASH 3 3 V Partial Plane Stratix II GX VCCpd HMCA HMCB SFPA SFPB Oscillators Driver VTT PowerNet Memory Termination XCVR_VCCA PowerNet TXVR VCCA XCVR_VCCHTX PowerNet XCVR VCCG XCVR_VCCR PowerNet XCVR VCCR XCVR_VCCT PowerNet XCVR VCCT XCVR VCCL VCCA PowerNet Stratix II GX EPLL FPLL 2 5 V Partial Plane Stratix II LVDS VCCio Marvell PHY 6A Switching R...

Page 70: ... also provide an optional on chip termination of 50 75 or 150 Ω QDRII Memory The QDRII interface signals do not have board level termination resistors Instead the QDRII interface is terminated using the 50 Ωoutput impedance settings available on both the Stratix II GX device and the QDRII SRAM device This approach simplifies board routing and lowers power consumption PCI Express The PCI Express si...

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