Demonstration Source Code Location
•
Quartus Project: TR4_PCIe0_Fundamental
•
Borland C++ Project: TR4_PCIe0_Fundamental \pc
FPGA Application Design
The PCI Express demonstration uses the basic I/O interface and DMA channel on the Terasic PCIe
IP to control I/O (Button/LED) and access two internal memories (RAM/FIFO) through the MUX
block.
Figure 4-4 Hardware Block Diagram of the PCIe Reference Design
PC Application Design
The application shows how to call the TERASIC_PCIE.DLL exported to API. To enumerate all
PCIe cards in system call, the software design defines some constants based on FPGA design shown
below:
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