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2–36

Reference Manual

Altera Corporation

Nios Development Board Stratix II Edition

May 2007

Board Components

Figure 2–17. Reset, Config Button

Reset Distribution

The EPM7256AE device takes a power-on reset pulse from the Linear
Technologies 1326 power-sense/reset-generator chip (U18) and
distributes it (through internal logic) to other reset pins on the board, that
include the following:

■

LAN91C111 (Ethernet MAC/PHY) reset

■

Flash memory reset

■

CompactFlash reset

■

Reset signals delivered to the expansion prototype connectors
(PROTO1 & PROTO2)

Starting Configuration

The following four methods start a configuration sequence:

1.

Board power-on

2.

Pressing the Reset, Config button (SW10).

3.

Asserting (driving 0 volts on) the

pld_reconfigreq_n

input pin

of the EPM7256AE device (U3 pin 94) from the FPGA (U60 pin H16).

4.

Pressing the Factory Config button (SW9).

Factory & User Configurations

The configuration controller can manage two separate FPGA
configurations stored in flash memory U5. These two configurations are
referred to as the factory configuration and the user configuration. A

Reset,
Config

SW10

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Summary of Contents for Nios Stratix II Edition

Page 1: ...101 Innovation Drive San Jose CA 95134 www altera com Development Board Version 6XX 40019R Document Version 1 3 Document Date May 2007 Nios Development Board Stratix II Edition Reference Manual ...

Page 2: ...ending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the ap plication or use of any information product or service d...

Page 3: ...5 Connector RJ1 2 13 Serial Connector J19 2 15 Expansion Prototype Connectors PROTO1 PROTO2 2 16 CompactFlash Connector CON3 2 23 PMC Connector JH1 JH2 2 26 Mictor Connector J25 2 29 Test Points TP1 TP8 2 31 EPCS64 Serial Configuration Device U69 2 32 Configuration Controller Device U3 2 33 Configuration Status LEDs 2 33 Configuration Reset Buttons 2 34 SW8 CPU Reset 2 34 SW9 Factory Config 2 35 S...

Page 4: ...Appendix A Restoring the Factory Configuration Introduction A 1 Reprogramming the Flash Memory A 1 Reprogramming the EPM7256AE Configuration Controller Device A 1 Appendix B Connecting to the Board via Ethernet Introduction B 1 Connecting the Ethernet Cable B 1 Connecting the LCD Screen B 2 Obtaining an IP Address B 2 LAN Connection B 3 DHCP B 3 Static IP Address B 3 Point to Point Connections B 4...

Page 5: ...2_io1 proto2_io29 proto2_io30 in Table 2 12 Changed Reference Designator for FPGA from U62 to U60 October 2006 1 1 Corrected statement LEDs D0 D7 turn on when driven to 0 not 1 June 2006 1 0 First publication Contact 1 Contact Method Address Technical support Website www altera com support Technical training Website www altera com training Email custrain altera com Product literature Website www a...

Page 6: ... within a document and titles of on line help topics are shown in quotation marks Example Typographic Conventions Courier type Signal and port names are shown in lowercase Courier type Examples data1 tdi input Active low signals are denoted by suffix n e g resetn Anything that must be typed exactly as it appears is shown in Courier type For example c qdesigns tutorial chiptrip gdf Also sections of...

Page 7: ...tton switches connected to FPGA user I O pins Eight LEDs connected to FPGA user I O pins Dual 7 segment LED display JTAG connectors to Altera devices via Altera download cables 50 MHz oscillator and zero skew clock distribution circuitry Power on reset circuitry General Description The Nios development board comes pre programmed with a Nios II processor reference design Hardware designers can use ...

Page 8: ...s II processor design in the FPGA wakes up and begins executing boot code from flash memory The board is factory programmed with a default reference design This reference design is a web server that delivers web pages via the Ethernet port For further information on the default reference design refer to Appendix B Connecting to the Board via Ethernet Proto 2 Expansion Prototype Connector User LEDs...

Page 9: ...e course of development you might overwrite or erase the flash memory space containing the default reference design Altera provides the flash image for the default reference design so you can return the board to its default state Refer to Appendix A Restoring the Factory Configuration for more information ...

Page 10: ...1 4 Reference Manual Altera Corporation Nios Development Board Stratix II Edition May 2007 Overview ...

Page 11: ...W0 SW3 Reset Config SW10 CON3 D0 D7 CPU Reset SW8 Factory Config SW9 Optional Power Optional Power Supply Supply Optional Power Supply PROTO1 J11 J12 J13 PROTO2 J15 J16 J17 Table 2 1 Nios Development Board Stratix II Edition Components Interfaces Board Designation Name Description U60 Stratix II FPGA EP2S60F672C3N device User Interface SW0 SW3 Push button switches Four momentary contact switches f...

Page 12: ...nnector CompactFlash connector for memory expansion JH1 JH2 PMC connector Expansion connector for a PCI mezzanine card J25 Mictor connector Mictor connector providing access to 27 I O pins on the FPGA Allows debugging Nios II systems using a First Silicon Solutions FS2 debug probe TP1 TP8 Test Points Test points providing access to eight FPGA I O pins J24 JTAG connector JTAG connection to the FPGA...

Page 13: ...play the current configuration status of the FPGA Clock Circuitry Y2 Oscillator 50 MHz clock signal driven to FPGA J4 External clock input Connector to FPGA clock pin Power Supply J26 DC power jack 16 V DC unregulated power source D34 Bridge rectifier Power rectifier allows for center negative or center positive power supplies J28 J29 J30 J33 and more Optional Power Supply External power supply ca...

Page 14: ...er refer to Configuration Controller Device U3 on page 2 33 f For Stratix II related documentation including pin out data for the EP2S60 device see the Altera Stratix II literature page at www altera com literature lit stx2 jsp Push Button Switches SW0 SW3 SW0 SW3 are momentary contact push button switches to provide stimulus to designs in the FPGA Refer to Figure 2 2 Each switch is connected to a...

Page 15: ... drives logic 0 the corresponding LED turns on Seven Segment LEDs U8 U9 U8 and U9 connect to the FPGA and each segment is individually controlled by a general purpose I O pin Refer to Figure 2 3 When a pin drives logic 0 the corresponding U8 and U9 LED turns on See Table 2 5 for pin out details Figure 2 3 Dual Seven Segment Display Table 2 4 LED Pin Table LED FPGA Pin Board Net Name D0 W15 pld_led...

Page 16: ...s II embedded processor as general purpose memory The factory programmed Nios II reference design identifies the SSRAM devices in its address space as a contiguous 2 MByte 32 bit word zero wait state main memory Table 2 5 Dual Seven Segment Display FPGA Pin U8 U9 Pin Pin Function Board Net Name U8 L8 10 a hex_0A L9 9 b hex_0B M7 8 c hex_0C M8 5 d hex_0D M5 4 e hex_0E M6 2 f hex_0F N4 3 g hex_0G N5...

Page 17: ... F26 38 NC A19 ssram_a6 F25 39 NC A20 ssram_a7 C17 42 A6 ssram_a8 C18 43 A7 ssram_a9 C19 44 A8 ssram_a10 C20 45 A9 ssram_a11 G26 46 A10 ssram_a12 G25 47 A11 ssram_a13 G24 48 A12 ssram_a14 G23 49 A13 ssram_a15 G21 50 A14 ssram_a16 G20 81 A15 ssram_a17 H26 82 A16 ssram_a18 H25 99 A17 ssram_a19 H24 100 A18 ssram_a20 B16 85 ADSC_N ssram_adsc_n H23 93 BE_n0 ssram_be_n0 J23 94 BE_n1 ssram_be_n1 K24 95 B...

Page 18: ...sram_d16 F22 19 D25 ssram_d17 F21 22 D26 ssram_d18 B23 23 D27 ssram_d19 D25 24 D28 ssram_d20 F24 25 D29 ssram_d21 H21 28 D30 ssram_d22 F19 29 D31 ssram_d23 B21 2 D16 ssram_d24 A21 3 D17 ssram_d25 A22 6 D18 ssram_d26 A24 7 D19 ssram_d27 C26 8 D20 ssram_d28 C25 9 D21 ssram_d29 J22 12 D22 ssram_d30 J21 13 D23 ssram_d31 J26 86 OE_n ssram_oe_n F17 87 WE_n ssram_we_n J25 84 ADSP_n ssram_adsp_n J24 83 AD...

Page 19: ... changed f See www cypress com for detailed information about the SSRAM chip DDR SDRAM Chip U63 U63 is a Micron DDR SDRAM chip The part number is MT46V16M16P 6T The DDR SDRAM pins are connected to the FPGA as shown in Table 2 7 Altera provides a DDR SDRAM controller that allows a Nios II processor to access the DDR SDRAM device as a large linearly addressable memory G18 88 GW_n ssram_gw_n A12 89 C...

Page 20: ..._dm0 B7 47 sdram_dm1 B10 29 sdram_a0 B9 30 sdram_a1 B8 31 sdram_a2 B6 32 sdram_a3 C5 35 sdram_a4 E11 36 sdram_a5 E10 37 sdram_a6 E9 38 sdram_a7 E8 39 sdram_a8 E7 40 sdram_a9 F11 28 sdram_a10 F10 41 sdram_a11 F8 42 sdram_a12 F10 26 sdram_ba0 G11 27 sdram_ba1 B3 22 sdram_cas_n F13 44 sdram_cke E12 24 sdram_cs_n A3 23 sdram_ras_n B4 21 sdram_we_n C4 46 sdram_clk_n C3 45 sdram_clk_p Table 2 7 DDR SDRA...

Page 21: ... to load the FPGA at power up Refer to Configuration Controller Device U3 on page 2 33 for related information A Nios II processor design in the FPGA can identify the 16 MByte flash memory in its address space and can program new data either new FPGA configuration data Nios II software or both into flash memory The Nios II development software includes subroutines for writing and erasing flash mem...

Page 22: ...V21 3 fe_a16 W22 54 fe_a17 W21 19 fe_a18 V24 18 fe_a19 V23 11 fe_a20 U24 12 fe_a21 U23 15 fe_a22 R24 2 fe_a23 D15 35 fe_d0 G15 37 fe_d1 E19 39 fe_d2 D20 41 fe_d3 G19 44 fe_d4 D19 46 fe_d5 E20 48 fe_d6 F20 50 fe_d7 H19 32 flash_cs_n H20 34 flash_oe_n V26 13 flash_rw_n H22 16 flash_wp_n K18 53 flash_byte_n 1 W25 17 flash_ry_by_n Note to Table 2 8 1 BYTE_n on U5 is pulled low to keep the flash memory...

Page 23: ...with the LAN91C111 Ethernet device Figure 2 4 Ethernet RJ 45 Connector Refer to Table 2 9 for connections between the FPGA and the MAC PHY device 1 The Ethernet MAC PHY device shares both address and data connections with the flash memory Table 2 9 Ethernet MAC PHY Pin Table FPGA Pin U4 Pin Pin Function Board Net Name 1 AB25 41 Address Enable enet_aen W20 43 Synchronous Ready enet_srdy_n W19 40 VL...

Page 24: ... U20 84 Address Line fe_a7 U19 85 Address Line fe_a8 T22 86 Address Line fe_a9 T21 87 Address Line fe_a10 T20 88 Address Line fe_a11 T19 89 Address Line fe_a12 U22 90 Address Line fe_a13 U21 91 Address Line fe_a14 V22 92 Address Line fe_a15 D15 107 Data Line fe_d0 G15 106 Data Line fe_d1 E19 105 Data Line fe_d2 D20 104 Data Line fe_d3 G19 102 Data Line fe_d4 D19 101 Data Line fe_d5 E20 100 Data Li...

Page 25: ... 232 voltage levels directly N21 70 Data Line fe_d13 M22 69 Data Line fe_d14 M21 68 Data Line fe_d15 M24 66 Data Line fe_d16 M23 65 Data Line fe_d17 L19 64 Data Line fe_d18 L18 63 Data Line fe_d19 L21 61 Data Line fe_d20 L20 60 Data Line fe_d21 L23 59 Data Line fe_d22 L22 58 Data Line fe_d23 K20 56 Data Line fe_d24 K19 55 Data Line fe_d25 K22 54 Data Line fe_d26 K21 53 Data Line fe_d27 J20 51 Data...

Page 26: ...totype Connectors PROTO1 PROTO2 PROTO1 and PROTO2 are standard footprint mechanically stable connectors that can be used for example as an interface to a special function daughter card Headers J11 J12 and J13 collectively form PROTO1 and J15 J16 and J17 collectively form PROTO2 The expansion prototype connector interface includes Table 2 10 Serial Connector Pin Table FPGA Pin J19 Pin Board Net Nam...

Page 27: ... signal that is asserted low Five regulated 3 3 V power supply pins 2 A total max load for both PROTO1 PROTO2 One regulated 5 0 V power supply pin 1 A total max load for both PROTO1 PROTO2 Numerous ground connections The PROTO1 expansion prototype connector shares FPGA I O pins with the CompactFlash connector CON3 Designs can use either the PROTO1 connector or the CompactFlash connector 1 Do not c...

Page 28: ...oto1_io21 29 proto1_io22 31 proto1_io24 33 proto1_io25 35 proto1_io27 37 proto1_io28 39 2 GND 4 proto1_io1 6 proto1_io3 8 proto1_io5 10 proto1_io7 12 proto1_io9 14 proto1_io11 16 proto1_io13 18 proto1_io15 20 NC 22 GND 24 GND 26 GND 28 proto1_io20 30 GND 32 proto1_io23 34 NC 36 proto1_io26 38 proto1_cardsel_n 40 GND J12 J11 1 Vunreg 1 NC 3 VCC3_3 5 VCC3_3 7 2 proto1_osc 9 3 proto1_pllclk 11 4 prot...

Page 29: ..._io5 E3 9 J11 proto1_io6 E4 10 J11 proto1_io7 F1 11 J11 proto1_io8 F2 12 J11 proto1_io9 F3 13 J11 proto1_io10 F4 14 J11 proto1_io11 G3 15 J11 proto1_io12 G4 16 J11 proto1_io13 H3 17 J11 proto1_io14 H4 18 J11 proto1_io15 J3 21 J11 proto1_io16 J4 23 J11 proto1_io17 G1 25 J11 proto1_io18 G2 27 J11 proto1_io19 H1 28 J11 proto1_io20 H2 29 J11 proto1_io21 K3 31 J11 proto1_io22 K4 32 J11 proto1_io23 J1 3...

Page 30: ...ansion Prototype Connector J15 J16 J17 J12 J7 3 J12 proto1_io40 L3 4 J12 proto1_io29 M1 5 J12 proto1_io30 M2 6 J12 proto1_io31 G6 7 J12 proto1_io32 G7 8 J12 proto1_io33 H5 9 J12 proto1_io34 H6 10 J12 proto1_io35 J5 11 J12 proto1_io36 J6 12 J12 proto1_io37 H7 13 J12 proto1_io38 H8 14 J12 proto1_io39 J13 U2 pin 19 9 J13 proto1_osc K6 11 J13 proto1_pllclk R26 13 J13 proto1_clkout Table 2 11 PROTO1 Pi...

Page 31: ...oto2_io21 29 proto2_io22 31 proto2_io24 33 proto2_io25 35 proto2_io27 37 proto2_io28 39 2 GND 4 proto2_io1 6 proto2_io3 8 proto2_io5 10 proto2_io7 12 proto2_io9 14 proto2_io11 16 proto2_io13 18 proto_2io15 20 NC 22 GND 24 GND 26 GND 28 proto2_io20 30 GND 32 proto2_io23 34 NC 36 proto2_io26 38 proto2_cardsel_n 40 GND J15 J16 1 Vunreg 1 NC 3 VCC3_3 5 VCC3_3 7 2 proto2_osc 9 3 proto2_pllclk 11 4 prot...

Page 32: ...1 9 J16 proto2_io6 W2 10 J16 proto2_io7 Y1 11 J16 proto2_io8 Y2 12 J16 proto2_io9 AA1 13 J16 proto2_io10 AA2 14 J16 proto2_io11 AB1 15 J16 proto2_io12 AB2 16 J16 proto2_io13 W3 17 J16 proto2_io14 W4 18 J16 proto2_io15 Y3 21 J16 proto2_io16 Y4 23 J16 proto2_io17 AA3 25 J16 proto2_io18 AA4 27 J16 proto2_io19 AB3 28 J16 proto2_io20 AB4 29 J16 proto2_io21 AC2 31 J16 proto2_io22 AC3 32 J16 proto2_io23 ...

Page 33: ...upported ATA hot swappable mode IDE IDE hard disk mode J15 AE3 3 J15 proto2_io40 Y9 4 J15 proto2_io29 AD7 5 J15 proto2_io30 W11 6 J15 proto2_io31 V12 7 J15 proto2_io32 AD8 8 J15 proto2_io33 Y11 9 J15 proto2_io34 W12 10 J15 proto2_io35 Y12 11 J15 proto2_io36 AD11 12 J15 proto2_io37 AE11 13 J15 proto2_io38 AB8 14 J15 proto2_io39 J17 U2 pin 18 9 J17 proto2_osc K7 11 J17 proto2_pllclk P2 13 J17 proto2...

Page 34: ...rd is not present the signal is pulled high through the pull up resistor Pin 41 of CON3 RESET is pulled up to 5 0 V through a 10 kΩ resistor and is controlled by the EPM7256AE configuration controller The FPGA can cause the configuration controller to assert RESET but the FPGA does not drive this signal directly The CompactFlash connector shares several FPGA I O pins with expansion prototype conne...

Page 35: ..._io14 H4 31 D15 proto1_io15 J4 35 IOWR_n proto1_io17 G1 34 IORD_n proto1_io18 G2 42 IORDY_n proto1_io19 K3 37 INTRQ proto1_io22 K4 24 IOCS16_n proto1_io23 J1 19 A1 proto1_io24 J2 20 A0 proto1_io25 K1 18 A2 proto1_io26 KK2 7 CS0_n proto1_io27 L2 45 DASP proto1_io28 L3 8 A10 proto1_io29 M1 46 PDIAG proto1_io30 M2 10 A9 proto1_io31 G6 11 A8 proto1_io32 G7 12 A7 proto1_io33 H5 14 A6 proto1_io34 H6 15 ...

Page 36: ...A must first be configured with a design that includes a PMC interface Damage to either the FPGA or daughter card can result if the FPGA is not configured correctly The factory programmed Nios II reference design does not include a PMC interface H8 43 INPACK_n proto1_io39 J7 44 REG_n proto1_io40 AE7 32 CS1_n cf_cs_n AE8 9 ATA_SEL_n cf_atasel_n AB12 5 Power supply enable cf_power 2 AB11 26 CD1_n cf...

Page 37: ...design configured in the FPGA As a general guideline if the PMC card power requirements exceed the specifications shown in Table 2 14 you must connect an external power source w When connecting an external power supply the fuse for the corresponding voltage should be removed from the development board to prevent the two power supplies from interfering with each other Refer to Power Supply Circuitr...

Page 38: ...mc_ad4 AF20 54 JH1 pmc_ad5 AD20 53 JH1 pmc_ad6 AF19 51 JH2 pmc_ad7 AE19 49 JH2 pmc_ad8 AD19 49 JH1 pmc_ad9 AF18 48 JH2 pmc_ad10 AC18 48 JH1 pmc_ad11 Y18 47 JH1 pmc_ad12 AF17 46 JH2 pmc_ad13 AC17 45 JH2 pmc_ad14 Y17 46 JH1 pmc_ad15 AE16 31 JH2 pmc_ad16 AD16 32 JH1 pmc_ad17 AB16 29 JH2 pmc_ad18 AA16 29 JH1 pmc_ad19 Y16 28 JH2 pmc_ad20 AF10 28 JH1 pmc_ad21 AD10 27 JH1 pmc_ad22 AF9 26 JH2 pmc_ad23 AC9...

Page 39: ...Nios II processor any on chip signals can be routed to I O pins and probed at J25 External scopes and logic analyzers can connect to J25 and analyze a large number of signals simultaneously AC6 52 JH1 pmc_be_n0 AF6 43 JH2 pmc_be_n1 AA10 32 JH2 pmc_be_n2 AC7 26 JH1 pmc_be_n3 AF8 43 JH1 pmc _par AE14 13 JH1 pmc_clk AA11 39 JH2 pmc_perr_n AC10 42 JH2 pmc_serr_n AA12 37 JH1 pmc_devsel_n AD9 38 JH2 pmc...

Page 40: ...s FS2 Inc connected to the Mictor connector For details see www fs2 com Figure 2 12 An ISA Nios T Connecting to the Mictor Connector J25 Five of the signals connect to both the JTAG pins on the FPGA U60 and the FPGA s JTAG connector J24 The JTAG signals have special usage requirements J25 and J24 cannot be used at the same time Figure 2 13 below shows connections from the Mictor connector to the F...

Page 41: ...connect to the configuration controller U3 Table 2 16 Mictor Connector Pin Table FPGA Pin J25 Pin Board Net Name AD15 5 mictor_clk T4 38 mictor0 T5 36 mictor1 U3 34 mictor2 U4 32 mictor3 T8 30 mictor4 T9 28 mictor5 V3 26 mictor6 V4 24 mictor7 U5 22 mictor8 U6 20 mictor9 T6 18 mictor10 T7 16 mictor11 U7 10 mictor12 U8 8 mictor13 V5 37 mictor14 V6 35 mictor15 V7 33 mictor16 V8 31 mictor17 WW5 29 mic...

Page 42: ...lash Controller component enables Nios II processor systems to access the EPCS device Nios II processor systems can read program code or data from the device and can write new data into the EPCS device U69 is blank by default The Quartus II software can program FPGA configuration data a pof file into U69 through an Altera download cable connected to J27 Alternately software running on a Nios II pr...

Page 43: ...nfiguration device U69 FPGA configuration data files are generated by the Quartus II software The Nios II integrated development environment IDE can write new configuration data to the board s flash memory f For complete details on the configuration controller connections see the board schematic For detailed information about the Altera EPM7256AE device see the MAX 7000 family literature at www al...

Page 44: ... FPGA LED4 Error Red If this LED is on then configuration was not transferred from flash memory into the FPGA This can happen if for example the flash memory does not contain either a valid user or factory configuration LED1 User Green This LED turns on when the user configuration is being transferred from flash memory and stays illuminated when the user configuration data is successfully loaded i...

Page 45: ...the FPGA with the factory configuration Refer to Figure 2 16 Figure 2 16 Factory Config Button SW10 Reset Config Reset Config SW10 is the power on reset button Refer to Figure 2 17 When SW10 is pressed a logic 0 is driven to the power on reset controller U18 Refer to Power Supply Circuitry on page 2 44 for more details Whenever SW10 is pressed the configuration controller attempts to reconfigure t...

Page 46: ...mpactFlash reset Reset signals delivered to the expansion prototype connectors PROTO1 PROTO2 Starting Configuration The following four methods start a configuration sequence 1 Board power on 2 Pressing the Reset Config button SW10 3 Asserting driving 0 volts on the pld_reconfigreq_n input pin of the EPM7256AE device U3 pin 94 from the FPGA U60 pin H16 4 Pressing the Factory Config button SW9 Facto...

Page 47: ... is a valid configuration image stored in the EPCS64 then the FPGA will only boot from the EPCS64 or from the factory image of flash memory when the SW9 switch is depressed The user segment of EPCS64 will be ignored If configuration from the EPCS64 does not succeed the configuration controller puts the FPGA into passive serial PS mode and attempts to load the user configuration from CFI flash memo...

Page 48: ...thout a valid factory configuration the configuration controller may not be able to successfully configure the FPGA If you alter the factory configuration you can restore the board to its factory programmed state Refer to Appendix B Restoring the Factory Configuration User Application Space The lower 8 MB of flash memory is the user application space This is free space for user designs to store co...

Page 49: ...64 KB starting at offset 0x00FF0000 This partition is for maintaining nonvolatile settings and data such as the MAC address and IP address for the factory programmed web server reference design Persistent data is technically no different than other application data but it is often convenient to think of certain data as independent from the user hardware or software JTAGConnectors J24 J5 The Nios d...

Page 50: ...gure 2 19 USB Blaster Connected to J24 JTAG Connector The FPGA s JTAG pins can also be accessed via the Mictor connector J25 The pins of J24 are connected directly to pins on J25 and care must be taken so that signal contention does not occur between the two connectors TMS TDI TCK TDO TRST To Mictor Connector J25 JTAG Signals JTAG Connector J24 FPGA U62 Pin 1 J24 ...

Page 51: ...rogram the configuration controller design in the EMP7256AE device Reprogramming the configuration controller can result in an inoperable development board f To restore the board to its factory programmed condition see Appendix B Restoring the Factory Configuration Figure 2 20 JTAG Connector J5 to MAX Device Clock Circuitry The Nios development board includes a 50 MHz free running oscillator Y2 an...

Page 52: ...llator from its socket Make sure to note the correct orientation of the oscillator before removing it osc_CLK0 osc_CLK1 sram_CLKIN sdram_CLKIN MAX U3 cpld_CLKOSC osc_CLK3 osc_CLK2 DDRSDRAM U63 SSRAM U74 sram_CLK PMC_CLK PMC JH1 JH2 FPGA U62 PLLs PROTO1 proto1_PLLCLK proto1_CLKOUT proto1_OSCCLK Mictor J25 mictor_CLK PROTO2 proto2_PLLCLK proto2_CLKOUT proto2_OSCCLK SMAExternal Input J4 Oscillator Y2...

Page 53: ...L Signal Source Board Net Name R1 CLK8p PLL3 PLL4 J25 pin 6 mictor_TRCLK R26 CLK2p PLL1 PLL2 J13 pin 13 proto1_CLKOUT P2 CLK10p PLL3 PLL4 J17 pin 13 proto2_CLKOUT B13 CLK12p PLL5 U2 pin 2 osc_CLK0 P25 CLK0p PLL1 PLL2 U2 pin 3 osc_CLK1 AC13 CLK7p PLL6 U2 pin 4 osc_CLK2 R3 CLK9p PLL3 PLL4 U2 pin 6 osc_CLK3 Table 2 22 FPGA Clock Output Pin Table FPGA Pin FPGA Pin Name PLL Signal Destination Board Net...

Page 54: ...AM chip and is not available on any connector or header The 1 2 V supply is used only as the power supply for the Stratix II device core VCCINT and it is not available on any connector or header The 12 0 V supply is provided for the PMC connectors JH1 and JH2 Refer to PMC Connector JH1 JH2 on page 2 26 for more details When workbench power supplies are connected to the board a corresponding fuse m...

Page 55: ...ograms Altera Nios II EDS installed version and then click Nios II Command Shell 2 From the examples directory change to the factory_recovery directory for your development kit cd factory_recovery niosII_stratixII_2s60_rohs 3 Run the flash restoration script restore_my_flash 4 Follow the script s instructions Reprogramming the EPM7256AE Configuration Controller Device If the configuration controll...

Page 56: ...tall path examples factory_recovery niosII_stratixII_2s60_rohs config_controller pof 4 In the Programmer turn on the Program Configure checkbox and click Start to reprogram the EPM7256AE device 5 Press the Factory Config button to perform a power on reset and reconfigure the FPGA from flash memory You should see the Factory LED turned on and activity on LEDs D0 through D7 Your board is now reconfi...

Page 57: ...Figure B 1 Web Server Reference Design Connecting the Ethernet Cable The Nios II development kit includes an Ethernet RJ45 cable and a male female RJ45 crossover adapter Before you connect these components you must decide how you want to use the network features of your board Select one of the two following connection methods 1 LAN Connection To use your Nios development board on a LAN for example...

Page 58: ...ct the other end of the RJ45 connector directly to the network Ethernet port on your host computer Connecting the LCD Screen The Nios II development kit includes a two line x 16 character LCD text screen The web server software displays useful status and progress messages on this display If you wish to use the network features of the board connect the LCD screen to expansion prototype connector J1...

Page 59: ... IP Address If the DHCP process fails the board uses a static IP address stored in flash memory You need to obtain a safe IP address in your LAN s subnet from your system administrator Once you know a safe IP address you can assign it to your board using the steps below These steps send IP configuration data to the board via an Altera JTAG download cable such as the USB Blaster cable 1 Install the...

Page 60: ... program then close the Nios II command shell 9 Press the SW8 button labeled CPU Reset to reboot the Nios II processor and start the web server using the new IP address The LCD screen displays the static IP address assigned to the board along with other status messages The web server is now ready to display pages using the IP address you assigned See Browsing to Your Board on page B 5 to continue ...

Page 61: ...e steps in Static IP Address on page B 3 Every time you reset the board the web server will attempt to obtain an IP address via DHCP which takes two minutes to time out You can abort the DHCP process or disable DHCP entirely by using the steps in Static IP Address on page B 3 Browsing to Your Board Once your board has a valid IP address obtained from either DHCP self configuration or from flash me...

Page 62: ...B 6 Reference Manual Altera Corporation Nios Development Board Stratix II Edition May 2007 ...

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