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Clock Resources

Table 2-1: MAX 10 Clock Resources

Clock Resource

Device

Number of Resources

Available

Source of Clock Resource

Dedicated clock input pins

• 10M02

• 10M04

• 10M08

8 single-ended or 4

differential

CLK[3..0][p,n]

pins on the

left and right of the I/O

banks

• 10M16

• 10M25

• 10M40

• 10M50

16 single-ended or 8

differential

CLK[7..0][p,n]

pins on the

top, left, bottom, and right of

the I/O banks

DPCLK

pins

All

DPCLK[3..0]

pins on the left

and right of the I/O banks

For more information about the clock input pins connections, refer to the pin connection guidelines.

Related Information

MAX 10 FPGA Device Family Pin Connection Guidelines

Global Clock Network Sources

Table 2-2: MAX 10 Clock Pins Connectivity to the GCLK Networks

CLK

Pin

GCLK

CLK0p

GCLK[0,2,4]

CLK0n

GCLK[1,2]

CLK1p

GCLK[1,3,4]

CLK1n

GCLK[0,3]

CLK2p

GCLK[5,7,9]

CLK2n

GCLK[6,7]

CLK3p

GCLK[6,8,9]

CLK3n

GCLK[5,8]

CLK4p

(1)

GCLK[10,12,14]

CLK4n

(1)

GCLK[11,12]

CLK5p

(1)

GCLK[11,13,14]

CLK5n

(1)

GCLK[10,13]

CLK6p

(1)

GCLK[15,17,19]

(1)

This only applies to 10M16, 10M25, 10M40, and 10M50 devices.

2-2

Clock Resources

UG-M10CLKPLL

2015.06.12

Altera Corporation

MAX 10 Clocking and PLL Architecture and Features

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Summary of Contents for MAX 10

Page 1: ...MAX 10 Clocking and PLL User Guide Subscribe Send Feedback UG M10CLKPLL 2015 06 12 101 Innovation Drive San Jose CA 95134 www altera com ...

Page 2: ... 2 10 PLL Locations 2 10 Clock Pin to PLL Connections 2 12 PLL Counter to GCLK Connections 2 12 PLL Control Signals 2 13 Clock Feedback Modes 2 14 PLL External Clock Output 2 17 ADC Clock Input from PLL 2 19 Spread Spectrum Clocking 2 19 PLL Programmable Parameters 2 19 Clock Switchover 2 22 PLL Cascading 2 26 PLL Reconfiguration 2 26 MAX 10 Clocking and PLL Design Considerations 3 1 Clock Network...

Page 3: ... IP Cores Legacy Parameter Editor 4 20 Obtaining the Resource Utilization Report 4 21 Internal Oscillator IP Core 4 21 IP Catalog and Parameter Editor 4 22 Specifying IP Core Parameters and Options 4 23 Files Generated for Altera IP Cores Legacy Parameter Editor 4 24 ALTCLKCTRL IP Core References 5 1 ALTCLKCTRL Parameters 5 1 ALTCLKCTRL Ports and Signals 5 2 ALTPLL IP Core References 6 1 ALTPLL Pa...

Page 4: ... 8 1 Internal Oscillator Parameters 8 1 Internal Oscillator Ports and Signals 8 1 Additonal Information for MAX 10 Clocking and PLL User Guide A 1 Document Revision History for MAX 10 Clocking and PLL User Guide A 1 TOC 4 Altera Corporation ...

Page 5: ...rs reconfiguration Bandwidth reconfiguration Programmable output duty cycle 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the proper...

Page 6: ... PLL cascading Reference clock switchover Drive the analog to digital converter ADC clock 1 2 PLLs Overview UG M10CLKPLL 2015 06 12 Altera Corporation MAX 10 Clocking and PLL Overview Send Feedback ...

Page 7: ...s When you use the CLK pins as differential inputs pair two clock pins of the same number to receive differential signaling Dual Purpose Clock Pins You can use the dual purpose clock DPCLK pins for high fan out control signals such as protocol signals TRDY and IRDY signals for PCI via GCLK networks The DPCLK pins are only available on the left and right of the I O banks 2015 Altera Corporation All...

Page 8: ...ion about the clock input pins connections refer to the pin connection guidelines Related Information MAX 10 FPGA Device Family Pin Connection Guidelines Global Clock Network Sources Table 2 2 MAX 10 Clock Pins Connectivity to the GCLK Networks CLK Pin GCLK CLK0p GCLK 0 2 4 CLK0n GCLK 1 2 CLK1p GCLK 1 3 4 CLK1n GCLK 0 3 CLK2p GCLK 5 7 9 CLK2n GCLK 6 7 CLK3p GCLK 6 8 9 CLK3n GCLK 5 8 CLK4p 1 GCLK 1...

Page 9: ...DPCLK2 GCLK 5 7 DPCLK3 GCLK 6 8 9 Figure 2 1 GCLK Network Sources for 10M02 10M04 and 10M08 Devices DPCLK2 DPCLK3 DPCLK0 DPCLK1 CLK 0 1 p n CLK 2 3 p n GCLK 0 4 GCLK 5 9 UG M10CLKPLL 2015 06 12 Global Clock Network Sources 2 3 MAX 10 Clocking and PLL Architecture and Features Altera Corporation Send Feedback ...

Page 10: ...skew and delay The clock control block has the following functions Dynamic GCLK clock source selection not applicable for DPCLK pins and internal logic input GCLK multiplexing GCLK network power down dynamic enable and disable Table 2 3 Clock Control Block Inputs Input Description Dedicated clock input pins Dedicated clock input pins can drive clocks or global signals such as synchronous and async...

Page 11: ...Disable C3 C4 Notes 1 The clkswitch signal can either be set through the configuration file or dynamically set when using the manual PLL switchover feature The output of the multiplexer is the input clock fIN for the PLL 2 The clkselect 1 0 signals are fed by internal logic You can use the clkselect 1 0 signals to dynamically select the clock source for the GCLK when the device is in user mode Onl...

Page 12: ... to feed a GCLK The clock control block supports static selection of the signal from internal logic Related Information ALTCLKCTRL Parameters on page 5 1 ALTCLKCTRL Ports and Signals on page 5 2 Global Clock Network Power Down You can disable the MAX 10 GCLK power down by using both static and dynamic approaches In the static approach configuration bits are set in the configuration file generated ...

Page 13: ... affected Figure 2 5 clkena Implementation clkena clkena_out clk_out clkin D Q Note The clkena circuitry controlling the C0 output of the PLL to an output pin is implemented with two registers instead of a single register Figure 2 6 Example Waveform of clkena Implementation with Output Enable The clkena signal is sampled on the falling edge of the clock clkin This feature is useful for application...

Page 14: ... can analyze this delay using the TimeQuest timing analyzer PLLs Architecture and Features PLL Architecture The main purpose of a PLL is to synchronize the phase and frequency of the voltage controlled oscillator VCO to an input reference clock Figure 2 7 MAX 10 PLL High Level Block Diagram Each clock source can come from any of the two or four clock pins located on the same side of the device as ...

Page 15: ... frequency fREF The VCO frequency is determined using the following equation fVCO fREF M fIN M N where fIN is the input clock frequency to the PLL and N is the pre scale counter The VCO frequency is a critical parameter that must be between 600 and 1 300 MHz to ensure proper operation of the PLL The Quartus II software automatically sets the VCO frequency within the recommended range based on the ...

Page 16: ...e following figures show the physical locations of the PLLs Every index represents one PLL in the device The physical locations of the PLLs correspond to the coordinates in the Quartus II Chip Planner 2 C counters range from 1 through 512 if the output clock uses a 50 duty cycle For any output clocks using a non 50 duty cycle the post scale counters range from 1 through 256 3 Only applicable if th...

Page 17: ...36packages only Figure 2 9 PLL Locations for 10M04 and 10M08 Devices Bank 8 Bank 1A Bank 2 Bank 6 Bank 5 PLL 1 1 PLL 2 2 Bank 7 Bank 3 Bank 4 Bank 1B Notes 1 Available on all packages except V81 package 2 Available on F256 F484 U324 and V81 packages only UG M10CLKPLL 2015 06 12 PLL Locations 2 11 MAX 10 Clocking and PLL Architecture and Features Altera Corporation Send Feedback ...

Page 18: ...o PLL Dedicated Clock Pin PLL CLK 0 1 p n PLL1 PLL3 CLK 2 3 p n PLL2 PLL4 CLK 4 5 p n PLL2 PLL3 CLK 6 7 p n PLL1 PLL4 PLL Counter to GCLK Connections Table 2 6 MAX 10 PLL Counter Connectivity to the GCLK Networks PLL Counter Output GCLK PLL1_C0 GCLK 0 3 15 18 PLL1_C1 GCLK 1 4 16 19 PLL1_C2 GCLK 0 2 15 17 PLL1_C3 GCLK 1 3 16 18 PLL1_C4 GCLK 2 4 17 19 PLL2_C0 GCLK 5 8 10 13 2 12 Clock Pin to PLL Con...

Page 19: ...fault When the PFD circuit is disabled the PLL output does not depend on the input clock and tends to drift outside of the lock window areset The areset signal is the reset or resynchronization input for each PLL The device input pins or internal logic can drive these input signals When you assert the areset signal the PLL counters reset clearing the PLL output and placing the PLL out of lock The ...

Page 20: ... 2 PLL Control Signals Parameter Settings on page 6 2 ALTPLL Ports and Signals on page 6 6 Clock Feedback Modes The MAX 10 PLLs support up to four different clock feedback modes Each mode allows clock multiplica tion and division phase shifting and programmable duty cycle The PLL fully compensates input and output delays only when you use the dedicated clock input pins associated with a given PLL ...

Page 21: ...luding any difference in delay between the following two paths Data pin to I O element register input Clock input pin to the PLL PFD input For all data pins clocked by a source synchronous mode PLL set the input pin to the register delay chain in the I O element to zero in the Quartus II software All data pins must use the PLL COMPENSATED logic option in the Quartus II software No Compensation Mod...

Page 22: ...duced by the GCLK network An internal clock in normal mode is phase aligned to the input clock pin In this mode the external clock output pin has a phase delay relative to the input clock pin The Quartus II software timing analyzer reports any phase difference between the two Figure 2 14 Example of Phase Relationship Between the PLL Clocks in Normal Compensation Mode PLL Reference Clock at the Inp...

Page 23: ...DB Mode PLL Reference Clock at the Input Pin PLL Clock at the Register Clock Port External PLL Clock Output at the Output Pin Phase Aligned PLL External Clock Output Each PLL in the MAX 10 devices supports one single ended clock output or one differential clock output Only the C0 output counter can feed the dedicated external clock outputs without going through the GCLK Other output counters can f...

Page 24: ...o the I O element The clock output pin pairs support the following I O standards Same I O standard as the standard output pins in the top and bottom banks LVDS LVPECL Differential high speed transceiver logic HSTL Differential SSTL The MAX 10 PLLs can drive out to any regular I O pin through the GCLK You can also use the external clock output pins as general purpose I O pins if you do not require ...

Page 25: ...uty cycle choices the Quartus II software uses the frequency input and the required multiply or divide rate The post scale counter value determines the precision of the duty cycle The precision is defined as 50 divided by the post scale counter value For example if the C0 counter is 10 steps of 5 are possible for duty cycle choices between 5 to 90 Combining the programmable duty cycle with program...

Page 26: ... you to implement large phase shifts quickly Fine Resolution Phase Shift Fine resolution phase shifts are implemented by allowing any of the output counters C 4 0 or the M counter to use any of the eight phases of the VCO as the reference clock This allows you to adjust the delay time with a fine resolution The following equation shows the minimum delay time that you can insert using this method F...

Page 27: ...periods td0 1 td0 2 1 8 tVCO tVCO 0 90 135 180 225 270 315 CLK0 CLK1 CLK2 45 Coarse Resolution Phase Shift Coarse resolution phase shifts are implemented by delaying the start of the counters for a predetermined number of counter clocks Figure 2 19 Coarse Resolution Phase Shift Equation C in this equation is the count value set for the counter delay time the initial setting in the PLL usage sectio...

Page 28: ...nitors the current reference clock If the current reference clock stops toggling the reference clock automatically switches to inclk0 or inclk1 clock Manual clock switchover The clkswitch signal controls the clock switchover When the clkswitch signal goes from logic low to high and stays high for at least three clock cycles the reference clock to the PLL switches from inclk0 to inclk1 or vice vers...

Page 29: ...e not valid if the frequency difference between inclk0 and inclk1 is greater than 20 The activeclock signal indicates which of the two clock inputs inclk0 or inclk1 is selected as the reference clock to the PLL When the frequency difference between the two clock inputs is more than 20 the activeclock signal is the only valid status signal Note Glitches in the input clock may cause the frequency di...

Page 30: ...ircuitry drives the clkbad 0 signal high Since the reference clock signal is not toggling the switchover state machine controls the multiplexer through the clksw signal to switch to the backup clock inclk1 inclk0 inclk1 muxout clkbad0 clkbad1 1 activeclock Note 1 Switchover is enabled on the falling edge of inclk0 or inclk1 depending on which clock is available In this figure switchover is enabled...

Page 31: ...k0 When the clkswitch signal goes high again the process repeats Figure 2 22 Example of Clock Switchover Using the clkswitch Manual Control inclk0 inclk1 muxout clkswitch activeclock clkbad0 clkbad1 Toinitiateamanualclockswitchoverevent bothinclk0andinclk1mustberunningwhen theclkswitchsignalgoeshigh The clkswitch signal and automatic switch work only if the clock being switched to is available If ...

Page 32: ... C1 C2 C3 C4 VCO Output VCO Output VCO Output VCO Output VCO Output VCO Output When cascading counters to implement a larger division of the high frequency VCO clock the cascaded counters behave as one counter with the product of the individual counter settings For example if C0 4 and C1 2 the cascaded value is C0 x C1 8 The Quartus II software automatically sets all the post scale counter values ...

Page 33: ...ut frequencies in a few microseconds You can also use this feature to adjust clock to out tCO delays in real time by changing the PLL output clock phase shift This approach eliminates the need to regenerate a configuration file with the new PLL settings Figure 2 24 PLL Reconfiguration Scan Chain This figure shows the dynamic adjustment of the PLL counter settings by shifting their new settings int...

Page 34: ...iguration Related Information Guideline mif Streaming in PLL Reconfiguration on page 3 5 PLL Dynamic Reconfiguration Implementation on page 4 10 PLL Dynamic Reconfiguration Parameter Settings on page 6 4 Provides more information about the ALTPLL IP core parameter settings in the Quartus II software ALTPLL_RECONFIG Parameters on page 7 1 Provides more information about the ALTPLL_RECONFIG IP core ...

Page 35: ...ck control block feeds any inclk port of another clock control block both clock control blocks must be able to be reduced to a single clock control block of equivalent functionality When you are using the glitch free switchover feature the clock you are switching from must be active If the clock is not active the switchover circuit cannot transition from the clock you originally selected 2015 Alte...

Page 36: ...g I O connectivity restrictions Guideline Self Reset The lock time of a PLL is the amount of time required by the PLL to attain the target frequency and phase relationship after device power up after a change in the PLL output frequency or after resetting the PLL A PLL might lose lock for a number of reasons such as the following causes Excessive jitter on the input clock Excessive switching noise...

Page 37: ...LL You can view the Quartus II software compilation report file to ensure the PLL bandwidth ranges do not overlap If the bandwidth ranges overlap jitter peaking can occur in the cascaded PLL scheme Note You can get an estimate of the PLL deterministic jitter and static phase error SPE by using the TimeQuest Timing Analyzer in the Quartus II software Use the SDC command derive_clock_uncertainty to ...

Page 38: ...nization period for the PLL to lock onto a new clock The exact amount of time it takes for the PLL to relock depends on the PLL configuration The phase relationship between the input clock to the PLL and output clock from the PLL is important in your design Assert areset for 10 ns after performing a clock switchover Wait for the locked signal or gated lock to go high before reenabling the output c...

Page 39: ...aming in single image mode Altera recommends using an external flash for dual image mode The MAX 10 devices do not support using both dual image mode and PLL reconfiguration with mif simultaneously Related Information PLL Reconfiguration on page 2 26 Guideline scandone Signal for PLL Reconfiguration scandone signal must be low before the second PLL reconfiguration For scandone signal to go low PLL...

Page 40: ...talog and parameter editor to locate and paramaterize Altera IP cores The IP Catalog lists installed IP cores available for your design Double click any IP core to launch the parameter editor and generate files representing your IP variation The parameter editor prompts you to specify an IP variation name optional ports and output file generation options The parameter editor generates a top level ...

Page 41: ...ation ShowIPonlyfortargetdevice Note The IP Catalog is also available in Qsys View IP Catalog The Qsys IP Catalog includes exclusive system interconnect video and image processing and other system level IP that are not available in the Quartus II IP Catalog For more information about using the Qsys IP Catalog refer to Creating a System with Qsys in the Quartus II Handbook Specifying IP Core Parame...

Page 42: ...ify options for processing the IP core files in other EDA tools 4 Click Generate HDL the Generation dialog box appears 5 Specify output file generation options and then click Generate The IP variation files generate according to your specifications 6 To generate a simulation testbench click Generate Generate Testbench System 7 To generate an HDL instantiation template that you can copy and paste i...

Page 43: ...vice Files Generated for Altera IP Cores Legacy Parameter Editor The Quartus II software version generates the following output for your IP core that uses the legacy parameter editor 4 4 Files Generated for Altera IP Cores Legacy Parameter Editor UG M10CLKPLL 2015 06 12 Altera Corporation MAX 10 Clocking and PLL Implementation Guides Send Feedback ...

Page 44: ...p IP core variation files your_ip qip or qsys System or IP integration file your_ip _generation rpt IP generation report your_ip bsf Block symbol schematic file your_ip ppf XML I O pin information file your_ip spd Combines individual simulation startup scripts 1 your_ip html Contains memory map your_ip sopcinfo Software tool chain integration file your_ip _syn v or vhd Timing resource estimation n...

Page 45: ...cify an IP variation name optional ports and output file generation options The parameter editor generates a top level Qsys system file qsys or Quartus II IP file qip representing the IP core in your project You can also parameterize an IP variation without an open project Use the following features to help you quickly locate and select an IP core Filter IP Catalog to Show IP for active device fam...

Page 46: ...specify IP core options and parameters in the parameter editor Refer to Specifying IP Core Parameters and Options Legacy Parameter Editors for configuration of IP cores using the legacy parameter editor 1 In the IP Catalog Tools IP Catalog locate and double click the name of the IP core to customize The parameter editor appears 2 Specify a top level name for your custom IP variation The parameter ...

Page 47: ... the current project automatically If you are prompted to manually add the qsys file to the project click Project Add Remove Files in Project to add the file 9 After generating and instantiating your IP variation make appropriate pin assignments to connect ports Figure 4 5 IP Parameter Editor ViewIPport andparameter details Applypresetparametersfor specificapplications SpecifyyourIPvariationname a...

Page 48: ... satisfactory note all of the values for the PLL from this report such as the M value N value charge pump current loop filter resistance and loop filter capacitance 7 In the schematic editor double click the ALTPLL instance in your design to open the ALTPLL parameter editor 8 On the Clock switchover page turn off Create an inclk1 input for a second input clock 9 Click Finish to update the PLL wrap...

Page 49: ... contain all of the initial counter values used in the PLL You can use these values for functional simulation in a third party simulator These parameter settings create no additional top level ports Related Information Programmable Bandwidth on page 2 19 Charge Pump and Loop Filter on page 4 13 Provides more information about the PLL components to update PLL bandwidth in real time Programmable Ban...

Page 50: ...ter rselodd For selecting the output clock duty cycle When the rbypass bit is set to 1 it bypasses the counter resulting in a division by one When this bit is set to 0 the PLL computes the effective division of the VCO output frequency based on the high and low time counters The PLL implements this duty cycle by transitioning the output clock from high to low on the rising edge of the VCO output c...

Page 51: ... 2 19 Scan Chain The MAX 10 PLLs have a 144 bit scan chain Table 4 1 PLL Component Reprogramming Bits Block Name Number of Bits Counter Control Bit Total C4 6 16 2 7 18 C3 16 2 7 18 C2 16 2 7 18 C1 16 2 7 18 C0 16 2 7 18 M 16 2 7 18 N 16 2 7 18 Charge Pump 9 0 9 Loop Filter 8 9 0 9 Total number of bits 144 6 LSB bit for C4 low count value is the first bit shifted into the scan chain 7 These two co...

Page 52: ... the following settings to update the PLL bandwidth in real time Charge pump ICP Loop filter resistor R Loop filter capacitor C Table 4 2 Charge Pump Bit Control CP 2 CP 1 CP 0 Setting Decimal 0 0 0 0 0 0 1 1 0 1 1 3 1 1 1 7 Table 4 3 Loop Filter Resistor Value Control LFR 4 LFR 3 LFR 2 LFR 1 LFR 0 Setting Decimal 0 0 0 0 0 0 0 0 0 1 1 3 0 0 1 0 0 4 0 1 0 0 0 8 1 0 0 0 0 16 1 0 0 1 1 19 UG M10CLKP...

Page 53: ...ettings on page 6 2 Bypassing PLL Counter Bypassing a PLL counter results in a multiplification M counter or a division N C0 to C4 counters factor of one Table 4 5 PLL Counter Settings Description PLL Scan Chain Bits 0 8 Settings LSB MSB PLL counter bypassed X X X X X X X X 1 9 PLL counter not bypassed X X X X X X X X 0 9 To bypass any of the PLL counters set the bypass bit to 1 The values on the ...

Page 54: ...NE a b c d The PHASESTEP signal is latched on the negative edge of SCANCLK a c and must remain asserted for at least two SCANCLK cycles Deassert PHASESTEP after PHASEDONE goes low On the second SCANCLK rising edge b d after PHASESTEP is latched the values of PHASEUPDOWN and PHASECOUNTERSELECT are latched The PLL starts dynamic phase shifting for the specified counters and in the indicated directio...

Page 55: ...ift step resolution might be larger than preferred for your design You can modify your phase shift resolution using the dynamic phase reconfiguration feature of the PLL If you want to modify the phase shift resolution without the dynamic phase reconfiguration feature enabled perform the following steps 1 Create an ALTPLL instance Make sure you specify the speed grade of your target device and the ...

Page 56: ...levant input ports phasecounterselect 3 0 phaseupdown phasestep and scanclk to constants if you prefer not to manually edit the PLL wrapper file using the Advanced PLL Parameters option Related Information Programmable Phase Shift on page 2 20 Files Generated for Altera IP Cores Legacy Parameter Editor The Quartus II generates the following output for IP cores that use the legacy MegaWizard parame...

Page 57: ...or replace the MegaWizard Plug In Manager for IP selection and parameterization beginning in Quartus II software version 14 0 Use the IP Catalog and parameter editor to locate and paramaterize Altera IP cores The IP Catalog lists installed IP cores available for your design Double click any IP core to launch the parameter editor and generate files representing your IP variation The parameter edito...

Page 58: ...specify IP core options and parameters in the parameter editor Refer to Specifying IP Core Parameters and Options Legacy Parameter Editors for configuration of IP cores using the legacy parameter editor 1 In the IP Catalog Tools IP Catalog locate and double click the name of the IP core to customize The parameter editor appears 2 Specify a top level name for your custom IP variation The parameter ...

Page 59: ...text editor click Generate HDL Example 8 Click Finish The parameter editor adds the top level qsys file to the current project automatically If you are prompted to manually add the qsys file to the project click Project Add Remove Files in Project to add the file 9 After generating and instantiating your IP variation make appropriate pin assignments to connect ports Figure 4 12 IP Parameter Editor...

Page 60: ...efer to the compilation reports in the Quartus II software To view the compilation reports for the ALTPLL_RECONFIG IP core in the Quartus II software follow these steps 1 On the Processing menu click Start Compilation to run a full compilation 2 After compiling the design on the Processing menu click Compilation Report 3 In the Table of Contents browser expand the Fitter folder by clicking the ico...

Page 61: ...ify an IP variation name optional ports and output file generation options The parameter editor generates a top level Qsys system file qsys or Quartus II IP file qip representing the IP core in your project You can also parameterize an IP variation without an open project Use the following features to help you quickly locate and select an IP core Filter IP Catalog to Show IP for active device fami...

Page 62: ...specify IP core options and parameters in the parameter editor Refer to Specifying IP Core Parameters and Options Legacy Parameter Editors for configuration of IP cores using the legacy parameter editor 1 In the IP Catalog Tools IP Catalog locate and double click the name of the IP core to customize The parameter editor appears 2 Specify a top level name for your custom IP variation The parameter ...

Page 63: ...editor click Generate HDL Example 8 Click Finish The parameter editor adds the top level qsys file to the current project automatically If you are prompted to manually add the qsys file to the project click Project Add Remove Files in Project to add the file 9 After generating and instantiating your IP variation make appropriate pin assignments to connect ports Figure 4 15 IP Parameter Editor View...

Page 64: ...ndor Simulator setup scripts simulator_setup_scripts your_ip IP core variation files your_ip qip or qsys System or IP integration file your_ip _generation rpt IP generation report your_ip bsf Block symbol schematic file your_ip ppf XML I O pin information file your_ip spd Combines individual simulation startup scripts 1 your_ip html Contains memory map your_ip sopcinfo Software tool chain integrat...

Page 65: ...k driven by this buffer On or Off Turn on this option if you want to create an active high clock enable signal to enable or disable the clock network 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All othe...

Page 66: ... Network Power Down on page 2 6 Clock Enable Signals on page 2 7 Guideline Clock Enable Signals on page 3 1 ALTCLKCTRL Ports and Signals Table 5 2 ALTCLKCTRL Input Ports for MAX 10 Devices Port Name Condition Description clkselect Optional Input that dynamically selects the clock source to drive the clock network that is driven by the clock buffer Input port 1 DOWNTO 0 wide If omitted the default ...

Page 67: ... supported for the global clock networks Table 5 3 ALTCLKCTRL Output Ports for MAX 10 Devices Port Name Condition Description outclk Required Output of the clock buffer Related Information Global Clock Control Block on page 2 4 Global Clock Network Power Down on page 2 6 Clock Enable Signals on page 2 7 Guideline Clock Enable Signals on page 3 1 UG M10CLKPLL 2015 06 12 ALTCLKCTRL Ports and Signals...

Page 68: ...e Which output clock will be compensated for C0 C1 C2 C3 or C4 Specify which PLL output port to compensate The drop down list contains all output clock ports for the selected device The correct output clock selection depends on the operation mode that you select For example for normal mode select the core output clock For zero delay buffer mode select the external output clock 2015 Altera Corporat...

Page 69: ...e You can use the programmable bandwidth feature with the clock switchover feature to get the PLL output settings that you desire You must set the bandwidth to Auto if you want to enable the spread spectrum feature Preset Low PLL with a low bandwidth has better jitter rejection but a slower lock time Medium PLL with a medium bandwidth has a balance between lock time and jitter rejection High PLL w...

Page 70: ...g loss of lock or when the clkswitch signal is asserted Perform the input clock switchover after number input clock cycles On or Off Turn on this option to specify the number of clock cycles to wait before the PLL performs the clock switchover The allowed number of clock cycles to wait is device dependent Create an activeclock output to indicate the input clock being used On or Off Turn on this op...

Page 71: ...mentation on page 4 15 Dynamic Phase Configuration Parameter Settings The parameter settings to enable the dynamic phase configuration feature are located on the PLL Reconfiguration page of the ALTPLL IP core parameter editor Table 6 5 Dynamic Phase Configuration Parameter Editor Settings Parameter Value Description Create optional inputs for dynamic phase reconfiguration On or Off Turn on this op...

Page 72: ...ut clock port in your ALTPLL instance The output clock port that is to be compensated for is enabled by default It cannot be disabled unless you select a different output clock port to be compensated for Enter output clock frequency Specify the frequency of the output clock signal Enter output clock parameters Specify the the output clock parameters instead of the frequency Clock multiplication fa...

Page 73: ...e requested multiplication and division factors are 205 and 1025 respectively the output clock frequency is calculated as 100 205 1025 20 MHz The actual settings reflect the simplest fraction the actual multiplication factor is 1 and the actual division factor is 5 ALTPLL Ports and Signals Table 6 7 ALTPLL Input Ports for MAX 10 Devices Port Name 10 Condition Description areset Optional Resets all...

Page 74: ...0 bits to select either the M or one of the C counters for phase adjustment One address map to select all C counters This signal is registered in the PLL on the rising edge of SCANCLK phasestep Optional Specifies dynamic phase shifting Logic high enables dynamic phase shifting phaseupdown Optional Specifies dynamic phase shift direction 1 UP 0 DOWN Signal is registered in the PLL on the rising edg...

Page 75: ...n the primary reference clock is not toggling correctly or you can manually initiate the clock switchover using the clkswitch input port c Required The clock output of the PLL clkbad Optional clkbad1 and clkbad0 ports check for input clock toggling If the inclk0 port stops toggling the clkbad0 port goes high If the inclk1 port stops toggling the clkbad1 port goes high 11 Replace the brackets in th...

Page 76: ...ck are the same or within the lock circuit tolerance When the difference between the two clock signals goes beyond the lock circuit tolerance the PLL loses lock phasedone Optional This output port indicates that dynamic phase reconfiguration is completed When phasedone signal is asserted it indicates to core logic that the phase adjustment is complete and PLL is ready to act on a possible second a...

Page 77: ...Related Information PLL Control Signals on page 2 13 6 10 ALTPLL Ports and Signals UG M10CLKPLL 2014 12 15 Altera Corporation ALTPLL IP Core References Send Feedback ...

Page 78: ...turning on Add ports to write to the scan chain from external ROM during run time Add ports to write to the scan chain from external ROM during run time On Off Turn on this option to take advantage of cycling multiple configuration files which are stored in external ROMs during user mode 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX...

Page 79: ... HDL black box file function name _bb v If the Generate netlist option is turned on the file for that netlist is also available function name _syn v Related Information Programmable Phase Shift on page 2 20 Dynamic Phase Configuration Implementation on page 4 15 PLL Reconfiguration on page 2 26 Dynamic Phase Configuration Implementation on page 4 15 ALTPLL_RECONFIG Ports and Signals Table 7 2 ALTP...

Page 80: ... C0 counter is 1 bit wide so data_in 0 is read for the value of this parameter If omitted the default value is 0 counter_type Optional Specifies the counter type An input port in the form of a 4 bit bus that selects which counter type should be selected for the corresponding operation read write or reconfig Refer to the counter_type 3 0 settings table for the mapping between the counter_type value...

Page 81: ...e clock and not on the same clock cycle as the read_param signal write_param Optional Writes the parameter specified with the counter_type and counter_param ports to the cache with the value specified on the data_in port When asserted the write_param signal indicates that the value on data_in should be written to the parameter specified by counter_type and counter_param The number of bits read fro...

Page 82: ...econfig signal is asserted the busy signal is only asserted on the following rising edge of the clock The busy signal is not asserted on the same clock cycle as the reconfig signal pll_areset_in Optional Input signal indicating that the PLL should be reset When asserted the pll_areset_in signal indicates the PLL IP core should be reset This port defaults to 0 if left unconnected When using the ALT...

Page 83: ...the case of a reconfiguration operation the busy signal remains high until the pll_areset signal is asserted and then deasserted pll_areset Required Drives the areset port on the PLL to be reconfigured The pll_areset port must be connected to the areset port of the ALTPLL IP core for the reconfiguration to function correctly This signal is active high The pll_ areset is asserted when pll_areset_in...

Page 84: ...scan data input to the PLL for the dynamically reconfigurable bits The pll_scandata port sends scandata to the PLL Any activity on this port can only be observed when the reconfig signal is asserted ALTPLL_RECONFIG Counter Settings Table 7 4 counter_type 3 0 Settings for MAX 10 Devices Counter Selection Binary Decimal N 0000 0 M 0001 1 CP LF 0010 2 VCO 0011 3 C0 0100 4 C1 0101 5 C2 0110 6 C3 0111 ...

Page 85: ...t scale 000 0 1 M N counters High count 000 0 8 Low count 001 1 8 Bypass 100 4 1 Mode odd even division 101 5 1 Nominal count 111 7 9 For even nominal count the counter bits are automatically set as follows high_count Nominalcount 2 low_count Nominalcount 2 For odd nominal count the counter bits are automatically set as follows high_count Nominalcount 1 2 low_count Nominalcount high_count odd even...

Page 86: ...CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor prod...

Page 87: ...o MAX 10 FPGA Device Datasheet September 2014 2014 09 22 Initial release 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property ...

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