• You can drive the devices before power up without damaging the device.
• I/O pins remain tri-stated during power up. The device does not drive out before or during power up,
therefore not affecting other buses in operation.
Drive MAX 10 Devices Before Power Up
Before or during power up or power down, you can drive signals into I/O pins, dedicated input pins, and
dedicated clock pins without damaging the MAX 10 devices.
The MAX 10 device supports any power-up or power-down sequence to simplify system-level design.
I/O Pins Remain Tri-stated During Power up
The output buffers of the MAX 10 device are turned off during system power up or power down. The
MAX 10 device family does not drive out until the device is configured and working in recommended
operating conditions. The I/O pins are tri-stated until the device enters user mode with a weak pull-up
resistor to V
CCIO
.
A possible concern for semiconductor devices in general regarding hot-socketing is the potential for latch
up. Latch up can occur when electrical subsystems are hot-socketed into an active system. During hot-
socketing, the signal pins may be connected and driven by the active system. This occurs before the power
supply can provide current to the V
CC
of the device and ground planes. This condition can lead to latch
up and cause a low-impedance path from V
CC
to ground in the device. As a result, the device extends a
large amount of current, possibly causing electrical damage.
The design of the I/O buffers and hot-socketing circuitry ensures that the MAX 10 device family is
immune to latch up during hot-socketing.
Related Information
MAX 10 FPGA Device Datasheet
Provides details about the MAX 10 ramp time requirements, internal oscillator clock frequency, and hot-
socketing specifications.
Hot-Socketing Feature Implementation
The hot-socketing feature tri-states the output buffer during the power-up (V
CCIO
or V
CC
power supplies)
or power-down event. The hot-socketing circuitry generates an internal
HOTSCKT
signal when V
CCIO
or
V
CC
is below the threshold voltage during power up or power down. The
HOTSCKT
signal cuts off the
output buffer to ensure that no DC current leaks through the pin (except for weak pull-up leaking). Each
I/O pin has the circuitry shown in the following figure. The hot-socketing circuit does not include
CONF_DONE
and
nSTATUS
pins to ensure that these pins are able to operate during configuration. Thus, it is
an expected behavior for these pins to drive out during power-up and power-down sequences.
2-10
Drive MAX 10 Devices Before Power Up
UG-M10PWR
2015.11.02
Altera Corporation
MAX 10 Power Management Features and Architecture
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