Enpirion
®
Power Evaluation Board User Guide
EN2340QI
PowerSoC
Figure 5: EN2340 Evaluation Board Schematic (NR1-NR3 are additional components on the back side)
C4
D1
S2A
Rev ision
Description
Date
Approv ed
+
C14
R12
12VIN
TP33
AGND
TP27
J7
J11
J6
VFB
C1
FB1
SCH 06904 w mods
PCB 06905
08
0
5
08
0
5
08
0
5
08
05
08
05
0805
C3
R13
R14
C10
TP30
TP31
TP6
TP3
J1
1
2
C3, 10 are 1206/0805
J10
VOUT
ENA
AVINO
AVINO
J4
TP9
1
2
TP15
TP14
C8
C9
N/U
R20
TP32
C2
POK
ENA
VIN
GND
GND
VOUT
Provision for Implementing
Adaptive Voltage Scaling
08
0
5
0805
R17
R18
PIN53
PIN53
PIN60
PIN60
C6
R8
R7
R3
R6
0402
0402
SW
C7
AVIN
0603
U1
EN2340
NC1
1
NC2
2
NC3
3
NC4
4
NC5
5
NC6
6
NC7
7
NC8
8
NC9
9
NC10
10
NC11
11
NC12
12
NC13
13
NC14
14
NC1
5
1
5
VOU
T
1
6
VOU
T
1
7
VOU
T
1
8
VOU
T
1
9
VOU
T
2
0
VOU
T
2
1
VOU
T
2
2
VOU
T
2
3
VOU
T
2
4
NC2
5
2
5
NC2
6
2
6
N
C
(SW
)27
2
7
N
C
(SW
)28
2
8
PGN
D
2
9
PGN
D
3
0
PGN
D
3
1
PGN
D
3
2
PGN
D
3
3
PGN
D
3
4
S_OUT
48
S_IN
47
BGND
46
VDDB
45
BTMP
44
PG
43
AVINO
42
PVIN
41
PVIN
40
PVIN
39
PVIN
38
PVIN
37
PVIN
36
PVIN
35
NC6
8
6
8
NC6
7
6
7
NC6
6
6
6
NC6
5
6
5
NC6
4
6
4
N
C
(SW
)63
6
3
N
C
(SW
)62
6
2
N
C
(SW
)61
6
1
AGN
D
6
0
NC5
9
5
9
FA
DJ
5
8
RCL
X
5
7
SS
5
6
EAOU
T
5
5
VF
B
5
4
AGN
D
5
3
AGN
D
5
2
AVI
N
5
1
EN
ABL
E
5
0
POK
4
9
0402
C19
C5
C20
EAOU
T
04
0
2
VFB
VF
B
R4
TP5
08
0
5
06
0
3
FADJ
08
0
5
J9
TP28
TP34
C16
R5
TP21
TP22
AVIN
C17
C18
08
05
EAOUT
VFB
08
05
08
05
12VIN
GND
GND
VOUT
R15
C12
0402
SOUT
SIN
C13
Preliminary Release
2/18/2013
CJR
C15
C21
R2
0805
0805
0805
NR3
Thru-hole
NR1
Thru-hole
NR2
0805
C12, 13, 15, 21
are 1206/0805
TP19
1
2
TP20
1
2
R10
12VIN
VOUT
R1
5.5V MAX
AVIN
08
0
5
T
P
10
04
0
2
TP8
TP7
J5
1
3
5
2
4
6
8
7
12VIN
ENA
ENA
08
05
T
P
29
TP17
1
2
TP18
1
2
R9
R19
VR1
5.1V
TP11
R16
TP12
12VIN
J3
1
2
3
AVIN
Short across R9
when all other
routing completed
TP4
AVIN
TP1
TP2
TP23
TP16
TP24
TP13
TP25
TP26
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