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DE1 User Manual

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Figure 4.5. Schematic diagram of the LEDs.

Signal Name

FPGA Pin No.

Description

SW[0]

PIN_L22

Toggle Switch[0]

SW[1]

PIN_L21

Toggle Switch[1]

SW[2]

PIN_M22

Toggle Switch[2]

SW[3]

PIN_V12

Toggle Switch[3]

SW[4]

PIN_W12

Toggle Switch[4]

SW[5]

PIN_U12

Toggle Switch[5]

SW[6]

PIN_U11

Toggle Switch[6]

SW[7]

PIN_M2

Toggle Switch[7]

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Summary of Contents for DE1

Page 1: ...Altera DE1 Board DE1 Development and Education Board User Manual Version 1 1 Copyright 2006 Altera Corporation...

Page 2: ...5 Overall Structure of the DE1 Control Panel 16 3 6 TOOLS Multi Port SRAM SDRAM Flash Controller 18 3 7 VGA Display Control 19 Chapter 4 Using the DE1 Board 24 4 1 Configuring the Cyclone II FPGA 24...

Page 3: ...f the DE1 package Figure 1 1 The DE1 package contents The DE1 package includes DE1 board USB Cable for FPGA programming and control CD ROM containing the DE1 documentation and supporting materials inc...

Page 4: ...rd Assembly To assemble the included stands for the DE1 board Assemble a rubber silicon cover as shown in Figure 1 2 for each of the six copper stands on the DE1 board The clear plastic cover provides...

Page 5: ...hnologies No 356 Sec 1 Fusing E Rd Jhubei City HsinChu County Taiwan 302 Email support terasic com Web www de1 terasic com Chapter 2 Altera DE1 Board This chapter presents the features and design char...

Page 6: ...DE1 board has many features that allow the user to implement a wide range of designed circuits from simple circuits to various multimedia projects The following hardware is provided on the DE1 board A...

Page 7: ...ftware is provided for a number of demonstrations that illustrate the advanced capabilities of the DE1 board In order to use the DE1 board the user has to be familiar with the Quartus II software The...

Page 8: ...multipliers 4 PLLs 315 user I O pins FineLine BGA 484 pin package Serial Configuration device and USB Blaster circuit Altera s EPCS4 Serial Configuration device On board USB Blaster for programming a...

Page 9: ...nced by a Schmitt trigger circuit Normally high generates one active low pulse when the switch is pressed Toggle switches 10 toggle switches for user inputs A switch causes logic 0 when in the DOWN cl...

Page 10: ...ly To power up the board perform the following steps 1 Connect the provided USB cable from the host computer to the USB Blaster connector on the DE1 board For communication between the host and the DE...

Page 11: ...to the UP position and connect the output of an audio player to the Line in connector on the DE1 board on your headset you should hear the music played from the audio player MP3 PC iPod or the like Yo...

Page 12: ...en installed to some other location on your computer system To activate the Control Panel perform the following steps 1 Connect the supplied USB cable to the USB Blaster port connect the 9V power supp...

Page 13: ...Figure 3 1 Quartus II Programmer window Figure 3 2 The DE1 Control Panel The concept of the DE1 Control Panel is illustrated in Figure 3 3 The IP that performs the control functions is implemented in...

Page 14: ...ithout worrying about how to build a Flash Memory Programmer 3 2 Controlling the LEDs and 7 Segment Displays A simple function of the Control Panel is to allow setting the values displayed on LEDs and...

Page 15: ...and Programmer The Control Panel can be used to write read data to from the SDRAM and SRAM chips on the DE1 board We will describe how the SDRAM may be accessed the same approach is used to access the...

Page 16: ...usual manner The Control Panel also supports loading files with a hex extension Files with a hex extension are ASCII text files that specify memory values using ASCII characters to represent hexadecim...

Page 17: ...the entire Flash memory is about 20 seconds Do not close the DE1 Control Panel in the middle of the operation To open the Flash memory control window shown in Figure 3 6 select the FLASH tab in the C...

Page 18: ...h the standard Windows dialog box asking for the destination file specify the desired file in the usual manner 3 5 Overall Structure of the DE1 Control Panel The DE1 Control Panel facility communicate...

Page 19: ...roller in C a USB command controller and a multi port SRAM SDRAM Flash controller Figure 3 7 The DE1 Control Panel block diagram Users can connect circuits of their own design to one of the User Ports...

Page 20: ...explained in Section 3 4 Then write a music file into the Flash memory You can use the file music wav in the directory DE1_demonstrations music on the DE1 System CD ROM 2 In the DE1 Control Panel sel...

Page 21: ...user to display an image via the VGA output port To illustrate this feature we will show how an image can be displayed on a VGA monitor Perform the following steps to display a default image Select th...

Page 22: ...nel and load the file picture dat into the SRAM Select the TOOLS page and choose Asynchronous 1 for the SRAM multiplexer port as shown in Figure 3 10 Click on the Configure button to activate the mult...

Page 23: ...e file by loading it into the SRAM chip or into an M4K memory block in the Cyclone II chip This requires generating a bitmap file which may be done as follows 1 Load the desired image into an image pr...

Page 24: ...tory as the original image file You can change the file name prefix from Raw_Data to another name by changing the File Name field in the displayed window 6 Raw_Data_Gray dat is the raw data that can b...

Page 25: ...0 Color Picture R G B N A Raw_Data_Gray Color Picture R G B optional BW Threshold Raw_Data_BW Raw_Data_BW txt Grayscale Picture N A N A Raw_Data_Gray Grayscale Picture N A BW Threshold Raw_Data_BW Raw...

Page 26: ...ming named after the IEEE standards Joint Test Action Group the configuration bit stream is downloaded directly into the Cyclone II FPGA The FPGA will retain this configuration as long as power is app...

Page 27: ...ing the EPCS4 in AS Mode Figure 4 2 illustrates the AS configuration set up To download a configuration bit stream into the EPCS16 serial EEPROM device perform the following steps Ensure that power is...

Page 28: ...device are connected directly to the Cyclone II FPGA Each switch provides a high logic level 3 3 volts when it is not pressed and provides a low logic level 0 volts when depressed Since the pushbutto...

Page 29: ...pin to a high logic level turns the LED on and driving the pin low turns it off A schematic diagram that shows the pushbutton and toggle switches is given in Figure 4 4 A schematic diagram that shows...

Page 30: ...nal Name FPGA Pin No Description SW 0 PIN_L22 Toggle Switch 0 SW 1 PIN_L21 Toggle Switch 1 SW 2 PIN_M22 Toggle Switch 2 SW 3 PIN_V12 Toggle Switch 3 SW 4 PIN_W12 Toggle Switch 4 SW 5 PIN_U12 Toggle Sw...

Page 31: ...me FPGA Pin No Description LEDR 0 PIN_R20 LED Red 0 LEDR 1 PIN_R19 LED Red 1 LEDR 2 PIN_U19 LED Red 2 LEDR 3 PIN_Y19 LED Red 3 LEDR 4 PIN_T18 LED Red 4 LEDR 5 PIN_V19 LED Red 5 LEDR 6 PIN_Y18 LED Red...

Page 32: ...Cyclone II FPGA Applying a low logic level to a segment causes it to light up and applying a high logic level turns it off Each segment in a display is identified by an index from 0 to 6 with the pos...

Page 33: ...Digit 2 1 HEX2 2 PIN_C2 Seven Segment Digit 2 2 HEX2 3 PIN_C1 Seven Segment Digit 2 3 HEX2 4 PIN_E3 Seven Segment Digit 2 4 HEX2 5 PIN_E4 Seven Segment Digit 2 5 HEX2 6 PIN_D3 Seven Segment Digit 2 6...

Page 34: ...sing the Expansion Header The DE1 Board provides two 40 pin expansion headers Each header connects directly to 36 pins on the Cyclone II FPGA and also provides DC 5V VCC5 DC 3 3V VCC33 and two GND pin...

Page 35: ...DE1 User Manual 33 Figure 4 10 Schematic diagram of the expansion headers Signal Name FPGA Pin No Description GPIO_0 0 PIN_A13 GPIO Connection 0 0...

Page 36: ...0 16 GPIO_0 17 PIN_C22 GPIO Connection 0 17 GPIO_0 18 PIN_D21 GPIO Connection 0 18 GPIO_0 19 PIN_D22 GPIO Connection 0 19 GPIO_0 20 PIN_E21 GPIO Connection 0 20 GPIO_0 21 PIN_E22 GPIO Connection 0 21...

Page 37: ...IO_1 17 PIN_C20 GPIO Connection 1 17 GPIO_1 18 PIN_D19 GPIO Connection 1 18 GPIO_1 19 PIN_D20 GPIO Connection 1 19 GPIO_1 20 PIN_E20 GPIO Connection 1 20 GPIO_1 21 PIN_F20 GPIO Connection 1 21 GPIO_1...

Page 38: ...fication for VGA synchronization and RGB red green blue data can be found on various educational web sites for example search for VGA signal timing Figure 4 12 illustrates the basic timing requirement...

Page 39: ...ng The pin assignments between the Cyclone II FPGA and the VGA connector are listed in Table 4 8 An example of code that drives a VGA display is described in Sections 5 2 and 5 3 Figure 4 12 VGA horiz...

Page 40: ...chip supports microphone in line in and line out ports with a sample rate adjustable from 8 kHz to 96 kHz The WM8731 is controlled by a serial I2C bus interface which is connected to pins on the Cycl...

Page 41: ...ments 4 8 RS 232 Serial Port The DE1 board uses the MAX232 transceiver chip and a 9 pin D SUB connector for RS 232 communications For detailed information on how to use the transceiver refer to the da...

Page 42: ...interface are shown in Table 4 11 Figure 4 17 PS 2 schematic Signal Name FPGA Pin No Description PS2_CLK PIN_H15 PS 2 Clock PS2_DAT PIN_J14 PS 2 Data Table 4 11 PS 2 pin assignments 4 10 Using SDRAM...

Page 43: ...DE1 User Manual 41 Figure 4 23 SDRAM schematic Figure 4 24 SRAM schematic...

Page 44: ...DRAM_ADDR 5 PIN_R5 SDRAM Address 5 DRAM_ADDR 6 PIN_P6 SDRAM Address 6 DRAM_ADDR 7 PIN_P5 SDRAM Address 7 DRAM_ADDR 8 PIN_P3 SDRAM Address 8 DRAM_ADDR 9 PIN_N4 SDRAM Address 9 DRAM_ADDR 10 PIN_W3 SDRAM...

Page 45: ...M Column Address Strobe DRAM_CKE PIN_N3 SDRAM Clock Enable DRAM_CLK PIN_U4 SDRAM Clock DRAM_WE_N PIN_R8 SDRAM Write Enable DRAM_CS_N PIN_T6 SDRAM Chip Select Table 4 16 SDRAM pin assignments Signal Na...

Page 46: ...10 SRAM_DQ 11 PIN_U9 SRAM Data 11 SRAM_DQ 12 PIN_R9 SRAM Data 12 SRAM_DQ 13 PIN_W8 SRAM Data 13 SRAM_DQ 14 PIN_V8 SRAM Data 14 SRAM_DQ 15 PIN_U8 SRAM Data 15 SRAM_WE_N PIN_AA10 SRAM Write Enable SRAM_...

Page 47: ...DR 17 PIN_AA20 FLASH Address 17 FL_ADDR 18 PIN_U14 FLASH Address 18 FL_ADDR 19 PIN_V14 FLASH Address 19 FL_ADDR 20 PIN_U13 FLASH Address 20 FL_ADDR 21 PIN_R13 FLASH Address 21 FL_DQ 0 PIN_AB16 FLASH D...

Page 48: ...monstrations on your computer perform the following 1 Copy the directory DE1_demonstrations into a local directory of your choice It is important to ensure that the path to your local directory contai...

Page 49: ...og file called DE1_Default v can be used as a template for other projects because it defines ports that correspond to all of the user accessible pins on the Cyclone II FPGA 5 2 Music Synthesizer Demon...

Page 50: ...The audio codec used on the DE1 board has two channels which can be turned ON OFF using SW1 and SW2 Figure 5 1 The Setup of the Music Synthesizer Demonstration Figure 5 2 Block diagram of the Music S...

Page 51: ...r Load the bit stream into FPGA Make sure all the switches SW 9 0 are set to 0 Down Position Press KEY1 on the DE1 board to start the music demo Press KEY0 on the DE1 board to reset the circuit Figure...

Page 52: ...RCK automatically As indicated in Figure 5 7 the I2C interface is used to configure the Audio CODEC The sample rate and gain of the CODEC are set in this manner and the data input from the line in por...

Page 53: ...such as an MP3 player or computer to the line in port blue color on the DE1 board Connect a headset speaker to the line out port green color on the DE1 board Load the bit stream into the FPGA You sho...

Page 54: ...WM8731 audio CODEC to play the music The audio CODEC is configured in the slave mode where external circuitry must provide the ADC DAC serial bit clock BCK and left right channel clock LRCK to the au...

Page 55: ...nto the FAT16 formatted SD Card Due to a limitation in the software used for this demonstration it is necessary to reformat the whole SD Card if any WAV file that has been copied onto the card needs t...

Page 56: ...ations in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arisin...

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