Altera Cyclone III FPGA Starter Kit, User Manual, Page: 22 / 32

4–2 Core Version a.b.c variable Altera Corporation
Cyclone III FPGA Starter Kit User Guide April 2007
Measuring Power
The design used for power measurement is a replicated set of randomly
filled ROMs that feed a multiplier block and a shift register that is fed by
a signal that changes every clock cycle. The states shown in
Tables 4–2
and 4–3 represent the percent of the full design used. As compiled, this
full design uses:
■
Logic elements: 22,493/24,624 (91%)
■
Combinational functions: 1,961/24,624 (8%)
■
Dedicated logic registers: 21,133/24,624 (86%)
■
Total registers: 21,133
■
Total pins: 73/216 (34%)
■
Total memory bits: 524,288/608,256 (86%)
■
Embedded Multiplier 9-bit elements: 128/132 (97 %)
■
Total PLLs: 1/4 (25%)
Measuring
Power
The design example can be located by default in < kit
install > \Examples\CIII_Power_Demo . Configure the FPGA with the
SOF found in the directory.
1
The input clock (
i_clk
PIN_B9) is the 50-MHz oscillator on the
board, which generates the input clock for the reference design
through a PLL
f
For more information on configuring the FPGA, refer to “FPGA
Configuration” on page 2–3 .
Current sense resistors (0.010 Ohms +/- 1%) are installed at location JP6
(FPGA core power) and JP3 (FPGA I/O power + other device I/O power).
With a digital multimeter set to the mV measurement range, the resistor
at location JP6 can be used to measure the core power. The resistor at
location JP3 can be used to measure the I/O power.
Table 4–3. LEDs Power State (Resources)
Displays
LEDs
State % of Design Used
MSB LSB
Resources LED4 LED3 00 25
%
01 50
%
10 75
%
11 100
%