Altera Cyclone III 3C120 Reference Manual Download Page 13

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Chapter 2: Board Components

2–3

Board Overview

Cyclone III 3C120 Development Board Reference Manual

Header

Speaker header.

D1, D3, D4

Ethernet PHY LEDs

Green Ethernet PHY LEDs. Illuminate when Ethernet PHY is using the
10/100/1000 Mbps (D1, D3, D4) connection speeds.

Duplex Ethernet PHY
LED

Green Ethernet PHY LED. Illuminates when Ethernet PHY is both sending and
receiving data.

Power LED

Blue LED indicates when power is applied to the board.

D7, D8

Ethernet PHY
transmit/receive activity
LEDs

Green LED. Illuminates when transmit/receive data is active from the Ethernet
PHY.

SW1

MAX II device control
DIP switch

Controls various features specific to the Cyclone III development board.

SW3

JTAG control switch

JTAG control DIP switch used to remove or include devices in the active JTAG
chain.

D17

SRAM active

SRAM active LED. Illuminates when the SRAM device is accessed.

D23

Flash active

Flash active LED. Illuminates when the flash device is accessed.

U28

Power display

Displays power measured by the MAX II CPLD.

D16

DDR2 LED

Indicates that the DDR2 top devices are active.

D11

DDR2 LED

Indicates that the DDR2 bottom devices are active.

Clock Circuitry

125 MHz

125-MHz clock oscillator used for the system clock.

50 MHz

50-MHz clock oscillator used for data processing.

24-MHz crystal

Cypress USB PHY.

6-MHz crystal

USB PHY FTDI reference clock.

24 MHz

MAX II device clock.

J10

SMA clock input

SMA connector that allows the provision of an external clock input.

J11

SMA clock output

SMA connector that allows the provision of an external clock output.

General User Input and Output

S1 through S4

User push buttons

Four 1.8-V push-button switches for user-defined, logic inputs.

CPU reset push button

One 1.8-V push-button switch for FPGA logic and CPU reset.

S6 and S7

Reset and factory
configuration push
buttons

Two 1.8-V push-button switches that control FPGA configuration from flash
memory.

D26 through D33

User LEDs

Eight user-defined LEDs.

SW5

PGM CONFIG SELECT

Rotary switch to select which FPGA configuration file to use in flash memory.

SW4

Power select rotary
switch

Power rail select for on-board power monitor.

U30

User display

User-defined, green 7-segment display.

Character LCD

14-pin LCD display.

J13

Graphics LCD

30-position dot matrix graphics LCD display.

Memory

U31

Flash

64 MB of flash memory with a 16-bit data bus.

Table 2–1.

Cyclone III Development Board (Part 2 of 3)

Board Reference

Type

Description

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Summary of Contents for Cyclone III 3C120

Page 1: ...101 Innovation Drive San Jose CA 95134 www altera com Cyclone III 3C120 Development Board Reference Manual Document Version 1 4 Document Date March 2009 Downloaded from Arrow com...

Page 2: ...plications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to ma...

Page 3: ...splay U28 2 18 Setup Elements 2 18 JTAG Control DIP Switch 2 19 MAX II Device Control DIP Switch 2 20 System Reset and Configuration Switches 2 20 POWER SELECT Rotary Switch 2 21 PGM CONFIG SELECT Rot...

Page 4: ...Mezzanine Connector 2 42 On Board Memory 2 48 DDR2 SDRAM 2 48 SRAM 2 54 Flash Memory 2 58 Power Supply 2 62 Power Measurement 2 64 Statement of China RoHS Compliance 2 64 Additional Information Revisi...

Page 5: ...e low static and dynamic power consumption Additionally with the support of the Quartus II software s PowerPlay technology designs are automatically optimized for power consumption Therefore the Cyclo...

Page 6: ...nation of low cost low power Cyclone III FPGA that supports high volume memory intensive designs Highest multiplier to logic ratio FPGA in the industry Lowest cost density and power optimized FPGA Qua...

Page 7: ...er LEDs One transmit receive LED TX RX per HSMC interface One configuration done LED Ethernet LEDs User 7 segment display Power consumption display Memory activity LEDs SRAM FLASH DDR2 Top DDR2 Bottom...

Page 8: ...esign_files schematic loopback_hsmc loopback_test_lowcost pdf Block Diagram Figure 1 1 shows the functional block diagram of the Cyclone III development board Figure 1 1 Cyclone III Development Board...

Page 9: ...precaution c Static Discharge Precaution Without proper anti static handling the board can be damaged Therefore use anti static handling precautions when touching the board Downloaded from Arrow com...

Page 10: ...al March 2009 Altera Corporation Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded...

Page 11: ...pliance on page 2 64 1 A complete set of board schematics a physical layout database and GERBER files for the Cyclone III development board are installed in the Cyclone III Development Kit documents d...

Page 12: ...uration Push Buttons S6 and S7 DDR2BOT_ACTIVE LED D16 50 MHz Clock Y5 125 MHz Clock Y4 24 MHz USB Blaster Clock Y3 JTAG Control DIP Switch SW3 Graphics LCD J13 HSMC Port B J9 Debug Header Shown HSMC P...

Page 13: ...ing Y1 24 MHz crystal Cypress USB PHY Y2 6 MHz crystal USB PHY FTDI reference clock Y3 24 MHz MAX II device clock J10 SMA clock input SMA connector that allows the provision of an external clock input...

Page 14: ...base T PHY device with an RGMII interface to the Cyclone III device J8 J9 HSMC Port A and Port B High speed mezzanine header allows for the connection of HSMC daughter cards Power Supply J2 DC power j...

Page 15: ...RAM MAX 1 8 V CMOS 78 Horizontal bank OCT calibration 1 8 V CMOS 4 2 Rup 2 Rdn Vertical bank OCT calibration 2 5 V CMOS 4 2 Rup 2 Rdn Passive serial configuration 2 5 V CMOS 2 DATAO DCLK Ethernet 2 5...

Page 16: ...lity The Cypress USB PHY is held in reset and is reserved for future use Each device has a shared path between the USB device and the MAX II CPLD The individual paths then drive to the FPGA separately...

Page 17: ...V CMOS 2 5 V CMOS 2 5 V CMOS To FPGA Table 2 5 MAX II Device Pin Out Note 1 Part 1 of 8 MAX II Pin Number I O Standard Signal Direction Schematic Signal Name P3 Input TCK L6 Input TDI M5 Output TDO N4...

Page 18: ...put FSA 17 P11 1 8 V Output FSA 18 R13 1 8 V Output FSA 19 T9 1 8 V Output FSA 2 M12 1 8 V Output FSA 20 R14 1 8 V Output FSA 21 N12 1 8 V Output FSA 22 T15 1 8 V Output FSA 23 P12 1 8 V Output FSA 24...

Page 19: ...idirectional FSD 29 T2 1 8 V Bidirectional FSD 3 E12 1 8 V Bidirectional FSD 30 C15 1 8 V Bidirectional FSD 31 N5 1 8 V Bidirectional FSD 4 R3 1 8 V Bidirectional FSD 5 P6 1 8 V Bidirectional FSD 6 R4...

Page 20: ...Input MAX_DIP 2 L14 1 8 V Input MAX_DIP 3 J5 2 5 V Output MAX_EMB M8 1 8 V Input MAX_EN J4 2 5 V Output MAX_ERROR J3 2 5 V Output MAX_FACTORY K1 2 5 V Output MAX_LOAD K13 1 8 V Input MAX_OEn M14 1 8 V...

Page 21: ...5 V Output PWR_SEG_DP E2 2 5 V Output PWR_SEG_E F4 2 5 V Output PWR_SEG_F E1 2 5 V Output PWR_SEG_G F2 2 5 V Output PWR_SEG_MINUS G4 2 5 V Input PWR_SEL 0 G1 2 5 V Input PWR_SEL 1 G5 2 5 V Input PWR_...

Page 22: ...V Bidirectional USB_PA7_SLCSn A4 2 5 V Input USB_PHY_CMD_DATA D6 2 5 V Output USB_PHY_EMPTY C13 2 5 V Bidirectional USB_PHY_FD 0 B16 2 5 V Bidirectional USB_PHY_FD 1 E11 2 5 V Bidirectional USB_PHY_F...

Page 23: ...ut USB_WR F10 Power VCCINT G11 Power VCCINT H8 Power VCCINT H10 Power VCCINT J7 Power VCCINT J9 Power VCCINT K6 Power VCCINT L7 Power VCCINT C1 Power VCCIO1 H6 Power VCCIO1 J6 Power VCCIO1 P1 Power VC...

Page 24: ...Table 2 5 1 For more information about the MAX II pin out refer to the Altera website at www altera com literature lit dp jsp Table 2 5 MAX II Device Pin Out Note 1 Part 8 of 8 MAX II Pin Number I O...

Page 25: ...rnal USB Blaster cable or equivalent to program either the MAX II CPLD or configure the Cyclone III FPGA Most users of the Cyclone III development board do not use the JTAG header at all and instead u...

Page 26: ...J6 1 Embedded USB Blaster 2 Cyclone III target device only 1 0 0 0 1 X 2 Embedded USB Blaster 2 4 Cyclone III device HSMC Port A 1 1 0 0 1 X 3 Embedded USB Blaster 2 4 Cyclone III device HSMC Port B...

Page 27: ...name and description Table 2 8 Board Specific LEDs Part 1 of 2 Board Reference LED Name Description D5 Power Illuminates when board power switch SW2 is on Requires 14 V to 20 V input to DC input jack...

Page 28: ...d such that pin 160 becomes grounded D19 HSMC Port B present Illuminates when HSMC Port B has a board or cable plugged such that pin 160 becomes grounded D17 SRAM active Illuminates when SRAM is being...

Page 29: ...om embedded USB Blaster JTAG chain 1 HSMA Port included in JTAG chain 0 HSMA Port not included in JTAG chain SW3 3 HSMB_BYPASS Includes or removes HSMB Port from embedded USB Blaster JTAG chain 1 HSMB...

Page 30: ...button switch FACTORY_CONFIG which is an input to the MAX II device The FACTORY_CONFIG pin forces a reconfiguration of the FPGA with the factory default FPGA design which is located at the base of fl...

Page 31: ...16 Power Select Rotary Switch Number Name Pin and Description Part 1 of 2 Number Schematic Signal Name Power Pin Name Description 0 1 2V_INT VCCINT FPGA core power 1 1 2V_VCCD VCCD_PLL FPGA PLL digita...

Page 32: ...Part 2 of 2 Number Schematic Signal Name Power Pin Name Description Table 2 17 Power Select Rotary Switch Component Reference and Manufacturing Information Board Reference Description Manufacturer Man...

Page 33: ...opment kit Figure 2 5 Cyclone III FPGA Clock Inputs Bank 8 1 8 V Bank 7 1 8 V Bank 3 1 8 V Bank 4 1 8 V Bank 6 2 5 V Bank 5 2 5 V Bank 1 2 5 V Bank 2 2 5 V HSMC Port A ENET PHY HSMA_CLK_IN_P2 HSMA_CLK...

Page 34: ...2 2 5 V HSMC Port A ENET PHY DDR2 DDR2 SRAM HSMA_CLK_OUT_P2 HSMA_CLK_OUT_N2 HSMA_CLK_OUT_P1 HSMA_CLK_OUT_N1 DDR2_CK_P0 HSMA_CLK_OUT0 HSMC Port B HSMB_CLK_OUT_IN0 HSMB_CLK_IN_P1 HSMB_CLK_IN_N1 HSMA_CLK...

Page 35: ...put J11 From Cyclone III device pin AE23 25 MHz reference clock This clock can change both speed and direction depending on the Ethernet link speed 10 100 1000 enet_rx_clk Input U5 Cyclone III device...

Page 36: ...name and corresponding Cyclone III pin number Table 2 24 lists the push button switch component reference and manufacturing information Table 2 23 Push Button Switch Signal Name and Function Board Ref...

Page 37: ...in 1 1 8 V USER_DIPSW0 AC14 SW6 pin 2 User defined DIP switch pin 2 1 8 V USER_DIPSW1 AD18 SW6 pin 3 User defined DIP switch pin 3 1 8 V USER_DIPSW2 AG23 SW6 pin 4 User defined DIP switch pin 4 1 8 V...

Page 38: ...ption Manufacturer Manufacturing Part Number Manufacturer Website D26 D33 Green LEDs 1206 SMT clear lens 2 1 V Lumex Inc SML LX1206GC TR www lumex com Table 2 29 HSMC User LEDs Board Reference Descrip...

Page 39: ...hannel D16 DDR2BOT_ACTIVE User defined but labeled DDR2BOT_ACTIVE in silkscreen for DDR2BOT memory channel Table 2 32 Memory User Defined LED Component Reference and Manufacturing Information Board Re...

Page 40: ...splay signal 1 8 V SEVEN_SEG_DP AD4 U30 pin 13 User defined display signal 1 8 V SEVEN_SEG_SEL1 B3 U30 pin 1 User defined display select signal 1 8 V SEVEN_SEG_SEL2 C5 U30 pin 10 User defined display...

Page 41: ...ption Manufacturer Manufacturing Part Number Manufacturer Website U30 7 segment green LED display Lumex Inc LDQ M2212R1 www lumex com Table 2 35 Power 7 Segment Display Component Reference and Manufac...

Page 42: ...data bus bit 6 2 5 V LCD_DATA6 V6 J22 pin 14 LCD data bus bit 7 2 5 V LCD_DATA7 AB3 J22 pin 4 LCD data command select 2 5 V LCD_D_Cn D27 J22 pin 5 LCD write enable 2 5 V LCD_D_WEn AC4 J22 pin 6 LCD c...

Page 43: ...ence and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Manufacturer Website J4 2 7 pin 100 mil vertical header Samtec TSM 107 01 G DV www samtec com 2 16...

Page 44: ...write enable 2 5 V LCD_WEn AC4 Note to Table 2 39 1 For the corresponding Cyclone III device pin number refer to the MAX II device pin out information in Table 2 5 on page 2 7 Downloaded from Arrow c...

Page 45: ...3 V2 Power supply for LCD drive V2 2 9 VS 24 V3 Power supply for LCD drive V3 7 9 VS 25 V4 Power supply for LCD drive V4 8 9 VS 26 V5 Power supply for LCD drive V5 VOUT 27 VR Voltage adjustment pin Ap...

Page 46: ...21 C63 C32 MS S0 S131 FR FRS CL CLS DOF OSC1 OSC2 D5 to D0 P S D6 SCL D7 SI C86 A0 CS2 CS1 WR Status Internal Bus Line RD RES COMM Downloaded from Arrow com Downloaded from Arrow com Downloaded from A...

Page 47: ...odule green LCD 1 Optrex America Inc F 51852GNFQJ LG ACN www optrex com Note to Table 2 41 1 The Cyclone III development board is shipped with either a blue or green Optrex LED display Downloaded from...

Page 48: ...ATA RD WR FIFO Receive Buffer 128 Bytes USB Protocol Engine USB Transceiver 3 3V LDO Regulator USB DPLL 6MHz Oscillator x8 Clock Multiplier Serial Interface Engine SIE RXF TXE EECS 3V3OUT EESK RSTOUT...

Page 49: ...3 FTDI Interface Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Manufacturer Web Site U8 FTDI USB device FTDI Ltd FT245BL www ftdi...

Page 50: ..._MDC N8 U5 pin 24 Management bus data 2 5 V ENET_MDIO L5 U5 pin 28 Reset 2 5 V ENET_RESETN AD2 U5 pin 2 RGMII interface receive clock 1 8 V ENET_RX_CLK B14 U5 pin 95 RGMII interface receive data bus b...

Page 51: ...is encoded on the rising edge of RX_CLK RX_ER XORed with RX_DV is encoded on the falling edge of RX_CLK ENET_RXD 3 0 RXD 3 0 RD 3 0 Receive data In 1000 base T and 1000 base X modes RXD 3 0 are prese...

Page 52: ...OS which is 3 3 V LVTTL compatible These pins can also be used as various differential I O standards including but not limited to LVDS mini LVDS and RSDS with up to 17 channels full duplex Resistor lo...

Page 53: ...D_N2 T3 J8 pin 62 LVDS RX bit 2n or CMOS I O data bit 15 LVDS or 2 5 V HSMA_RX_D_N2 U4 J8 pin 65 LVDS TX bit 3p or CMOS I O data bit 16 LVDS or 2 5 V HSMA_TX_D_P3 R3 J8 pin 66 LVDS RX bit 3p or CMOS I...

Page 54: ...ta bit 53 LVDS or 2 5 V HSMA_RX_D_P11 K2 J8 pin 121 LVDS TX 11n or CMOS I O data bit 54 LVDS or 2 5 V HSMA_TX_D_N11 J3 J8 pin 122 LVDS RX 11n or CMOS I O data bit 55 LVDS or 2 5 V HSMA_RX_D_N11 K1 J8...

Page 55: ...ic Signal Name Cyclone III Device Pin Number J9 pin 33 Management serial data 2 5 V HSMB_SDA H26 J9 pin 34 Management serial clock 2 5 V HSMB_SCL H25 J9 pin 35 JTAG clock signal 2 5 V FPGA_JTAG_TCK P5...

Page 56: ...RX 7p or CMOS I O data bit 33 LVDS or 2 5 V HSMB_RX_D_P7 P27 J9 pin 91 LVDS TX 7n or CMOS I O data bit 34 LVDS or 2 5 V HSMB_TX_D_N7 V28 J9 pin 92 LVDS RX 7n or CMOS I O data bit 35 LVDS or 2 5 V HSMB...

Page 57: ...HSMB_RX_D_P15 AB27 J9 pin 145 LVDS RX 15n or CMOS I O data bit 70 LVDS or 2 5 V HSMB_TX_D_N15 Y22 J9 pin 146 LVDS TX 15n or CMOS I O data bit 71 LVDS or 2 5 V HSMB_RX_D_N15 AB28 J9 pin 149 LVDS RX 16p...

Page 58: ...m Wattage 12 V 1 0 A 12 0 W 3 3 V 2 0 A 6 6 W Table 2 50 HSMC Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Manufacturer Website...

Page 59: ...yclone III Device Pin Number U25 U26 pin K8 Differential clock 0n SSTL18 Class 1 DDR2_CK_N0 AF14 U11 U12 pin K8 Differential clock 1n SSTL18 Class 1 DDR2_CK_N1 G11 U13 pin F8 Differential clock 2n SST...

Page 60: ...U11 pin H9 Data 37 SSTL18 Class 1 DDR2_DQ37 C12 U11 pin F1 Data 38 SSTL18 Class 1 DDR2_DQ38 E14 U11 pin F9 Data 39 SSTL18 Class 1 DDR2_DQ39 D13 U26 pin H1 Data 4 SSTL18 Class 1 DDR2_DQ4 AD17 U11 pin C...

Page 61: ...1 DDR2_DQ71 D22 U26 pin C8 Data 8 SSTL18 Class 1 DDR2_DQ8 AG18 U26 pin C2 Data 9 SSTL18 Class 1 DDR2_DQ9 AG17 U26 pin F7 Data strobe 0 SSTL18 Class 1 DDR2_DQS0 AE18 U26 pin B7 Data strobe 1 SSTL18 Cl...

Page 62: ...T_CSn AC21 U25 U26 pin K9 Bottom on die termination enable SSTL 18 Class I DDR2BOT_ODT AE24 U25 U26 pin K7 Bottom row address strobe SSTL 18 Class I DDR2BOT_RASn AE21 U25 U26 pin K3 Bottom write enabl...

Page 63: ...51 DDR2 Interface I O Part 5 of 5 Board Reference Description I O Standard Schematic Signal Name Cyclone III Device Pin Number Table 2 52 DDR2 Interface Component Reference and Manufacturing Informat...

Page 64: ...3 U24 pin C3 Address bit 6 DWORD aligned 1 8 V FSA6 AF26 U23 U24 pin C4 Address bit 7 DWORD aligned 1 8 V FSA7 AF4 U23 U24 pin D4 Address bit 8 DWORD aligned 1 8 V FSA8 AD8 U23 U24 pin H2 Address bit...

Page 65: ...Data bit 28 1 8 V FSD28 C9 U24 pin F2 Data bit 29 1 8 V FSD29 E7 Table 2 53 SRAM Interface I O Part 2 of 3 Board Reference Description I O Standard SchematicSignal Name Cyclone III Device Pin Number...

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Page 68: ...FSA2 AA13 U31 pin A2 Address bus bit 3 word aligned 1 8 V FSA3 AC10 U31 pin B2 Address bus bit 4 word aligned 1 8 V FSA4 Y15 U31 pin D3 Address bus bit 5 word aligned 1 8 V FSA5 AF22 U31 pin C3 Addre...

Page 69: ...ble 2 5 on page 2 7 Table 2 56 Flash Interface I O Part 2 of 2 Board Reference Description I O Standard Schematic Signal Name Cyclone III Device Pin Number Downloaded from Arrow com Downloaded from Ar...

Page 70: ...EBE1 0x00E0 0000 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com...

Page 71: ...cturer Manufacturer Part Number Manufacturer Website U31 64 MB of flash memory Spansion LLC S29GL512N11FFIV1 www spansion com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow...

Page 72: ...d from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com D...

Page 73: ...RE R MEASURE R MEASURE R MEASURE R MEASURE R MEASURE R MEASURE Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloa...

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Page 78: ...d a b c and so on Numbered steps indicate a list of items when the sequence of the items is important such as the steps listed in a procedure Bullets indicate a list of items when the sequence of the...

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Summary of Contents for Cyclone III 3C120

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Altera Cyclone III 3C120, Reference Manual, Page: 13 / 80

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Summary of Contents for Cyclone III 3C120

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