4–6
Chapter 4: Parameter Settings
PCI Express and PCI Capabilities Parameters
Arria V GZ Hard IP for PCI Express
November 2012
Altera Corporation
PCI Express and PCI Capabilities Parameters
This group of parameters defines various capability properties of the IP core. Some of
these parameters are stored in the
. The byte offset within the
indicates the parameter address.
lists these
parameters.
Table 4–6. Capabilities Registers (Part 1 of 2)
Parameter
Possible
Values
Default Value
Description
Device Capabilities
Maximum
payload size
128 bytes
256 bytes,
512 bytes,
1024 bytes,
2048 bytes
128 bytes
Specifies the maximum payload size supported. This parameter
sets the read-only value of the max payload size supported field of
the Device Capabilities register (0x084[2:0]). Address:
Tags supported
32
64
32 - Avalon-ST
Indicates the number of tags supported for non-posted requests
transmitted by the Application Layer. This parameter sets the
values in the Device Control register (0x088) of the PCI Express
capability structure described in
The Transaction Layer tracks all outstanding completions for
non-posted requests made by the Application Layer. This
parameter configures the Transaction Layer for the maximum
number to track. The Application Layer must set the tag values in
all non-posted PCI Express headers to be less than this value.
Values greater than 32 also set the extended tag field supported bit
in the Configuration Space Device Capabilities register. The
Application Layer can only use tag numbers greater than 31 if
configuration software sets the Extended Tag Field Enable bit of the
Device Control register. This bit is available to the Application Layer
on the
tl_cfg_ctl
output signal as
cfg_devcsr[8]
.
The Avalon-MM Arria V GZ Hard IP for PCI Express always
supports 8 tags. You do not need to configure this parameter.