Altera Arria II GX Reference Manual Download Page 29

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Chapter 2: Board Components

2–21

Clock Circuitry

February 2011

Altera Corporation

Arria II GX FPGA Development Board Reference Manual

Clock Circuitry

This section describes the board's clock inputs and outputs.

Arria II GX FPGA Clock Inputs

The development board has two types of clock inputs—global clock inputs and
transceiver reference clock inputs.

Figure 2–6

shows the Arria II GX FPGA development board clock inputs.

Table 2–20

shows the external clock inputs for the Arria II GX FPGA development

board.

Figure 2–6. Arria II GX FPGA Development Board Clock Inputs

Q 0

Q 1

Q 2

Q 3

6 B

6 A

5 A

5 B

PLL 1

PLL 2

PLL 3

PLL 4

EP2AGX125EF35

Control signals route

to MAX II

155.52 M

CLK_SEL

REFCLK INPUT

SMA

(LVPECL)

2-to-4 buffer

MAX II CPLD

EPM2210 System Controller

25 MHz
Crystal

3 .3 V

Low Jitter Clock

Generator*

(Default 125 MHz)
CDCM61004RHB

XIN 2

(LVDS)

3 .3 V

(LVPECL)

CLK 2 _ RSTn

CLK 2 _ CE

CLK 2 _ OS 1

CLK 2 _ OS 0

CLK 2 _ PR 1
CLK 2 _ PR 0
CLK 2 _ OD 2
CLK 2 _ OD 1
CLK 2 _ OD 0

3 .3 V

XIN 1

7 6 5 4 3 2 1 0

IN_

]

)

HSMA CLK_IN_P[2]/N[2]

(LVDS)

HSMB_CLK_IN0

HSMA_CLK_IN0

* CDCM6100x can be set to output frequencies

of 100 MHz, 125 MHz, 156.25 MHz.

PLL

25 MHz
Crystal

CLOCK_SMA

SMA

100 M

50 M

ENET_RX_CLK

(2.5 V)

Low Jitter Clock

Generator*

(Default 100 MHz)
CDCM61001RHB

(2.5 V)

(LVDS)

)

Table 2–20. Arria II GX FPGA Development Board Clock Inputs (Part 1 of 2)

Source

Schematic Signal Name

Pin

I/O Standard

Description

U25

CLK_155_P

R29

LVPECL

155.52 MHz oscillator which drives the
transceiver Q2 reference clock input with
100



OCT.

CLK_155_N

R30

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Summary of Contents for Arria II GX

Page 1: ...Innovation Drive San Jose CA 95134 www altera com MNL 01047 1 2 Reference Manual Arria II GX FPGA Development Board Subscribe Arria II GX FPGA Development Board Reference Manual Downloaded from Arrow...

Page 2: ...rants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time...

Page 3: ...17 Status Elements 2 17 Setup Elements 2 18 Board Settings DIP Switch 2 18 JTAG Chain Header 2 19 PCI Express Control DIP Switch 2 20 Reset Configuration Push button Switches 2 20 Clock Circuitry 2 21...

Page 4: ...tion Appendix A Board Revision History Single Die Flash Version Differences A 1 Additional Information Document Revision History Info 1 How to Contact Altera Info 1 Typographic Conventions Info 2 Down...

Page 5: ...riety of HSMCs available from Altera and various partners f To see a list of the latest HSMCs available or to download a copy of the HSMC specification refer to the Development Board Daughtercards pag...

Page 6: ...On board USB BlasterTM for use with the Quartus II Programmer On Board ports Two HSMC expansion ports HSMC port B is only populated when a EP2AGX260 FPGA device is installed One gigabit Ethernet port...

Page 7: ...eset push button switch One load image push button switch to program the FPGA from flash memory One image select push button switch select image to load from flash memory Two general user push button...

Page 8: ...1 Arria II GX FPGA Development Board Block Diagram Port B Port A 128 Mbyte DDR3 x16 2x16 LCD Push button Switches DIP Switch LEDs CPLD 64 Mbyte Flash 2 Mbyte SSRAM x8 Edge 1 Gbyte DDR2 SODIMM x64 Giga...

Page 9: ...and installing the demonstration software refer to the Arria II GX FPGA Development Kit User Guide This chapter consists of the following sections Board Overview Featured Device Arria II GX Device on...

Page 10: ...nector J6 Gigabit Ethernet Port J8 JTAG Chain Header J9 Fan Power J13 SSRAM x36 Memory U22 PCI Express Mode Set SW3 PCI Express Mode Status D24 D26 Table 2 1 Arria II GX FPGA Development Board Compone...

Page 11: ...s 100 M U30 Programmable oscillator 100 MHz default Programmable oscillator with a default frequency of 100 00 MHz The frequency is programmable using the MAX II CPLD EPM2210 System Controller For gen...

Page 12: ...SB type B connector USB interface for programming the FPGA through embedded USB Blaster JTAG via a type B USB cable J8 Gigabit Ethernet RJ 45 connector which provides a 10 100 1000 Ethernet connection...

Page 13: ...GX Device Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Manufacturer Website U19 FPGA Arria II GX F1152 124K LES leadfree Altera...

Page 14: ...DIMM 64 Port 1 8 V SSTL 120 8 Diff 8 DQS MAX Bus 1 5 V CMOS 8 Flash SRAM FSM Bus 2 5 V CMOS 82 PCI Express 8 2 5 V CMOS XCVR 41 1 REFCLK 8 XCVR HSMC Port A 2 5 V CMOS LVDS XCVR 104 4 XCVR 17 LVDS 5 Cl...

Page 15: ...on the MAX II CPLD EPM2210 System Controller The signal names and functions are relative to the MAX II device U32 Figure 2 3 MAX II CPLD EPM2210 System Controller Block Diagram Information Register Em...

Page 16: ...ower monitor frequency csense_csn 0 J14 Power monitor 0 chip select csense_csn 1 H15 Power monitor 1 chip select csense_sck H16 Power monitor serial peripheral interface SPI clock csense_sdi H14 Power...

Page 17: ...K21 FSM bus address fsm_a 16 A12 L21 FSM bus address fsm_a 17 B12 F25 FSM bus address fsm_a 18 C12 F26 FSM bus address fsm_a 19 B13 G23 FSM bus address fsm_a 2 E10 D29 FSM bus address fsm_a 20 A13 H21...

Page 18: ...bus data fsm_d 5 D4 E18 FSM bus data fsm_d 6 C6 G19 FSM bus data fsm_d 7 D5 F19 FSM bus data fsm_d 8 E6 D21 FSM bus data fsm_d 9 D14 D23 FSM bus data hsma_psnt_n A10 U3 HSMC port A present hsmb_psnt_...

Page 19: ...le sram_mode J3 FSM bus SSRAM burst sequence selection sram_zz B3 B27 FSM bus SSRAM power sleep mode usb_disablen K2 DIP embedded USB Blaster disable usb_led K1 Embedded USB Blaster active Table 2 7 M...

Page 20: ...sh button switch PB5 FPGA Programming over Embedded USB Blaster The board implements a USB Blaster using a USB Type B connector J6 a FTDI USB 2 0 PHY device U15 and an Altera MAX IIZ CPLD U10 This all...

Page 21: ...A HSMC Port B GPIO TMS GPIO TDO GPIO TDI JTAG Master GPIO DISABLE JTAG Master Slave JTAG Master Slave Installed HSMC Card Installed HSMC Card TCK TMS TDI TDO TCK TMS TDI TDO TCK TMS TDI TDO TCK TMS T...

Page 22: ...ware This method restores the development board to its factory default settings Other methods to program the flash memory can be used as well including the Nios II processor f For more information on...

Page 23: ...ERROR MAX_LED LOAD DIP0 DIP1 DIP1 FACTORY USER LOAD LCD_PWRMON USB_DISABLEn CLK_EN CLK_SEL MAX_RESETn LOAD_IMAGE RESET_CONF IGN IMAGE_SEL FACTORY CONFIG_LED0 CONFIG_LED1 CONFIG_LED2 DIP Switch Table 2...

Page 24: ...option bits 32 0x0001 FFFF 0x0001 8000 Board information 32 0x0001 7FFF 0x0001 0000 Ethernet option bits MAC address 32 0x0000 FFFF 0x0000 8000 User design reset vector 32 0x0000 7FFF 0x0000 0000 Tab...

Page 25: ...0 System Controller fails to configure the FPGA Driven by the MAX II CPLD EPM2210 System Controller D11 D12 D13 CONFIG 2 0 Green LEDs Illuminates to indicate which hardware page loads from flash memor...

Page 26: ...Lite On LTST C170KGKT www us liteon com opto index html D16 Red LED Lite On LTST C170KRKT www us liteon com opto index html D18 Blue LED Lite On LTST C170TBKT www us liteon com opto index html Table 2...

Page 27: ...Chain Header Controls Switch Schematic Signal Name Description Default 1 MAX_JTAG_EN ON Bypass MAX II CPLD EPM2210 System Controller OFF MAX II CPLD EPM2210 System Controller in chain OFF 2 HSMA_JTAG...

Page 28: ...atic Signal Name Description Default 1 PCIE_PRSNT2n_x1 ON Enable x1 presence detect OFF Disable x1 presence detect ON 2 PCIE_PRSNT2n_x4 ON Enable x4 presence detect OFF Disable x4 presence detect ON 3...

Page 29: ...2 1 0 H S M A _ C L K _ IN _ P 1 N 1 LVDS HSMA CLK_IN_P 2 N 2 LVDS HSMB_CLK_IN0 HSMA_CLK_IN0 CDCM6100x can be set to output frequencies of 100 MHz 125 MHz 156 25 MHz PLL 5 PLL 6 25 MHz Crystal C L K...

Page 30: ...e installed HSMC port B cable or board PCI Express Edge PCIE_REFCLK_P AE29 HCSL High Speed Current Steering Logic HCSL input from the PCI Express edge connector PCIE_REFCLK_N AE30 Notes to Table 2 20...

Page 31: ...PIO Samtec HSMC HSMA_CLKOUT0 P10 2 5 V FPGA CMOS output or GPIO Samtec HSMC HSMA_CLKOUT_P1 AD7 LVDS or 2 5 V LVDS output or two 2 5 V CMOS outputs HSMA_CLKOUT_N1 AD6 Samtec HSMC HSMA_CLKOUT_P2 V12 LVD...

Page 32: ...and Manufacturing Information Board Reference Description Manufacturer Manufacturer Part Number Manufacturer Website U25 156 25 MHz LVPECL Saw Oscillator Epson EG 2102CA 155 5200M DGPA www eea epson c...

Page 33: ...to PB3 Push Button switch Dawning Precision Co TS A02SA 2 S100 http www dawning2 com tw company php Table 2 25 User defined DIP Switch Schematic Signal Names and Functions Board Reference Description...

Page 34: ...C170KGKT www us liteon com opto index html Table 2 29 HSMC User defined LED Schematic Signal Names and Functions Board Reference Description Schematic Signal Name I O Standard Arria II GX Device Pin...

Page 35: ...data bus LCD_DATA1 H3 J3 9 LCD data bus LCD_DATA2 E1 J3 10 LCD data bus LCD_DATA3 F2 J3 11 LCD data bus LCD_DATA4 D2 J3 12 LCD data bus LCD_DATA5 D1 J3 13 LCD data bus LCD_DATA6 C2 J3 14 LCD data bus...

Page 36: ...5 R W H L H Data read module to MPU L Data write MPU to module 6 E H H to L Enable 7 14 DB0 DB7 H L Data bus software selectable 4 bit or 8 bit mode Table 2 32 LCD Pin Definitions and Functions Part 2...

Page 37: ...CI Express Reference Clock Levels VMAX 1 15 V VCROSS MAX 550 mV VCROSS MIN 250 mV VMIN 0 30 V REFCLK REFCLK Table 2 34 PCI Express Pin Assignments Schematic Signal Names and Functions Part 1 of 2 Boar...

Page 38: ...SL AE29 J14 A14 Motherboard reference clock PCIE_REFCLK_N AE30 J14 A11 Reset PCIE_PERSTn LVTTL N1 J14 B11 Wake signal PCIE_WAKEn C30 J14 B5 SMB clock PCIE_SMBCLK M18 J14 B6 SMB data PCIE_SMBDAT D27 x1...

Page 39: ...O N20 U24 28 Device reset ENET_RESETn M20 U24 2 RGMII receive clock ENET_RX_CLK V6 U24 95 RGMII receive data ENET_RX_D 0 E21 U24 92 RGMII receive data ENET_RX_D 1 E24 U24 93 RGMII receive data ENET_RX...

Page 40: ...r Bank 1 has every third pin removed as done in the QSH DP QTH DP series Bank 2 and bank 3 have all the pins populated as done in the QSH QTH series Figure 2 10 shows the bank arrangement of signals w...

Page 41: ...Transceiver RX bit 0 HSMA_RX_P0 U33 J2 31 Transceiver TX bit 0n HSMA_TX_N0 T32 J2 32 Transceiver RX bit 0n HSMA_RX_N0 U34 J2 33 Management serial data HSMA_SDA 2 5 V R1 J2 34 Management serial clock H...

Page 42: ...S TX bit 7 or CMOS bit 32 HSMA_TX_D_P7 V4 J2 90 LVDS RX bit 7 or CMOS bit 33 HSMA_RX_D_P7 Y2 J2 91 LVDS TX bit 7n or CMOS bit 34 HSMA_TX_D_N7 V3 J2 92 LVDS RX bit 7n or CMOS bit 35 HSMA_RX_D_N7 W1 J2...

Page 43: ...LVDS TX bit 15n or CMOS bit 70 HSMA_TX_D_N15 V10 J2 146 LVDS RX bit 15n or CMOS bit 71 HSMA_RX_D_N15 AB7 J2 149 LVDS TX bit 16 or CMOS bit 72 HSMA_TX_D_P16 U11 J2 150 LVDS RX bit 16 or CMOS bit 73 HS...

Page 44: ...H32 J1 32 Transceiver RX bit 0n HSMB_RX_N0 J34 J1 33 Management serial data HSMB_SDA 2 5 V AK27 J1 34 Management serial clock HSMB_SCL AJ27 J1 35 JTAG clock signal JTAG_TCK L24 J1 36 JTAG mode select...

Page 45: ...AG7 J1 90 Dedicated CMOS I O bit 33 HSMB_D33 AF7 J1 91 Dedicated CMOS I O bit 34 HSMB_D34 AE7 J1 92 Dedicated CMOS I O bit 35 HSMB_D35 AE8 J1 95 Dedicated CMOS I O bit 36 HSMB_D36 AF8 J1 96 Dedicated...

Page 46: ...0 HSMB_D70 G4 J1 146 Dedicated CMOS I O bit 71 HSMB_D71 C6 J1 149 Dedicated CMOS I O bit 72 HSMB_D72 D6 J1 150 Dedicated CMOS I O bit 73 HSMB_D73 C5 J1 151 J1 152 J1 155 LVDS or CMOS clock out 2 or CM...

Page 47: ...of 4 Board Reference Description Schematic Signal Name I O Standard Arria II GX Device Pin Number Table 2 39 HSMC Connector Component Reference and Manufacturing Information Board Reference Descriptio...

Page 48: ...ress select DDR3_RAS_n A13 U13 T2 Reset DDR3_RST_n G18 U13 L3 Write enable DDR3_WE_n A15 U13 J7 Clock P DDR3_CLK_P Differential 1 5 V SSTL Class I B13 U13 K7 Clock N DDR3_CLK_N B12 Downloaded from Arr...

Page 49: ...ta strobe N byte lane 1 DDR3_DQS_N1 E12 Table 2 40 DDR3 Pin Assignments Schematic Signal Names and Functions Part 2 of 2 Board Reference Description Schematic Signal Name I O Standard Arria II GX Devi...

Page 50: ...s select DDR2_RAS_n AH12 J7 197 EEPROM serial clock DDR2_SCL J7 195 EEPROM serial data DDR2_SDA J7 109 Write enable DDR2_WE_n AM6 J7 30 Clock P0 DDR2_CLK_P0 Differential 1 8 V SSTL Class I AJ7 J7 32 C...

Page 51: ...ane 2 DDR2_DQSN2 AP22 J7 61 Data bus byte lane 3 DDR2_DQ24 AN21 J7 63 Data bus byte lane 3 DDR2_DQ25 AM21 J7 73 Data bus byte lane 3 DDR2_DQ26 AE18 J7 75 Data bus byte lane 3 DDR2_DQ27 AP18 J7 62 Data...

Page 52: ...lane 6 DDR2_DQ52 AF16 J7 160 Data bus byte lane 6 DDR2_DQ53 AL14 J7 174 Data bus byte lane 6 DDR2_DQ54 AE16 J7 176 Data bus byte lane 6 DDR2_DQ55 AL11 J7 170 Write mask byte lane 6 DDR2_DM6 AC15 J7 16...

Page 53: ...nd Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Manufacturer Website J7 200 pin DDR2 SODIMM socket Tyco Electronics 1 1734075 1 www tycoelectronics com...

Page 54: ...Names and Functions Part 2 of 3 Board Reference Description Schematic Signal Name I O Standard Arria II GX Device Pin Number Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow c...

Page 55: ...2 45 SSRAM Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Manufacturer Website U22 Standard synchronous pipelined SCD 512K 36 200...

Page 56: ...D8 Address bus FSM_A17 F25 U23 A7 Address bus FSM_A18 F26 U23 B7 Address bus FSM_A19 G23 U23 C7 Address bus FSM_A20 H21 U23 C8 Address bus FSM_A21 M13 U23 A8 Address bus FSM_A22 P7 U23 G1 Address bus...

Page 57: ...ber Table 2 47 Flash Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Manufacturer Website U23 512 MB synchronous flash Numonyx PC28...

Page 58: ...A A2VCC A2GX Core VCC 0 9 V 5 710 A 0 9 V 5 781 A A2VCCD PLL A2GX Digital PLL 0 9 V 0 071 A BEAD 5 0V_MONITOR x2 LT2418 5 0 V 0 010 A TPS71550 0 010 A 3 3V HSMC Port A and B 2 LVDS Clock Buffer 3 3 V...

Page 59: ...8A I O power HSMA 4 A2VCCPD 2 5 VCCPD I O pre drivers and input buffers 5 A2VCCIO_B3A_B4 1 8 VCCIO_B3A Bank 3A I O power DDR2 SODIMM VCCIO_B4 Bank 4 I O power DDR2 SODIMM 6 A2VCCIO_B7A 1 5 VCCIO_B7A B...

Page 60: ...at the concentration of the hazardous substance of at least one of all homogeneous materials in the parts is above the relevant threshold of the SJ T11363 2006 standard but it is exempted by EU RoHS D...

Page 61: ...ng silicon version Engineering silicon Speed grade C5NES device September 2009 Initial release Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com D...

Page 62: ...wnloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arro...

Page 63: ...so contact your local Altera sales office or sales representative Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Down...

Page 64: ...ttention A question mark directs you to a software help system with related information f The feet direct you to another document or website with related information c A caution calls attention to a c...

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