40GBASE-KR4 Ethernet MAC and PHY IP
The Altera 40G Ethernet MAC and PHY IP core is implemented in compliance with the IEEE 802.3ba 2010
Higher Speed Ethernet Standard. It is including Auto-Negotiation (AN), Link Training (LT) and Forward
Error Correction (FEC). This module handles the frame encapsulation and flow of data between a client
logic and Ethernet network via a 40GbE Ethernet PCS and PMA (PHY). In the TX direction, the MAC
accepts client frames, inserts inter-packet gap (IPG), preamble, start of frame delimiter (SFD), header,
padding, and checksum before passing them to the PHY. The PHY encodes the MAC frame as required
for reliable transmission over the media to the remote end. Similarly, in the RX direction, the MAC
accepts frames from the PHY, performs checks, updates statistics counters, strips out the CRC, preamble,
and SFD, and passes the rest of the frame to the client.
Packet Client with Random Packet Generator and Monitor
:
The Packet Client includes a Packet Generator and a Packet Monitor. These modules have 256-bit
Avalon-ST interface for the data-path and connect to the 40G Ethernet MAC. There is also a 32-bit
Avalon-MM configuration and status interface associated with both the generator and monitor. The
generator can generate random packets. Monitor parses all packets received from MAC and checks the
integrity of the packets.
Terminal System Controller
(sterm.exe):
This reference design provides a windows terminal program sterm.exe which can run on a PC (windows
based operating system). User must provide byte addresses in order to access registers on chip using
this interface.
Summary of Contents for 40GBASE-KR4
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