Altera 40GBASE-KR4 Quick User Manual Download Page 4

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System Overview and Functional Description

The hardware platform consists of three sub-systems:



The 40GBase-KR4 MAC and PHY IP



Packet Client with random packet generator and monitor



System Console for configuration and control of the system

This system can be represented by the following diagram:

Figure 1 System Overview

Summary of Contents for 40GBASE-KR4

Page 1: ...Ethernet Reference Design Quick User guide Example on 40GBASE KR4 Stratix V GX Signal Integrity Development Board Date 05 03 2016 Revision 1 0...

Page 2: ...d PHY IP 5 40Gbps Ethernet MAC and PHY IP Overview 6 Quick Start Guide 7 Signal Integrity Stratix V GT Edition Setup 9 Compile Build Load and Run the Software 9 Viewing the Result 11 System Monitor Pa...

Page 3: ...ely control test and monitor 40Gbps Ethernet packets This hardware demonstration reference design offers the following features Auto Negotiation AN as defined in Clause 63 only negotiation to 40GBASE...

Page 4: ...form consists of three sub systems The 40GBase KR4 MAC and PHY IP Packet Client with random packet generator and monitor System Console for configuration and control of the system This system can be r...

Page 5: ...RX direction the MAC accepts frames from the PHY performs checks updates statistics counters strips out the CRC preamble and SFD and passes the rest of the frame to the client Packet Client with Rando...

Page 6: ...s adapter then provides a standard Avalon ST interface for the MAC client The MAC connects to the PHY core over XLGMII interface The 40G Ethernet IP core can be demonstrated as the following simplifie...

Page 7: ...Edition v12 0 0 or above with clock control feature if the software says current active Quartus version isn t the correct version then the board is broken you need to switch to another board Hardware...

Page 8: ...onents are provided in detail as shown below Figure 3 Hardware Setup The Signal Integrity Stratix V GT development board requires minimum hardware setup Switch 6 SW6 all 4 pin need to set to logic 0 c...

Page 9: ...ck Control Compile Build Load and Run the Software 1 Open the project file alt_e40_avalon_top_sv_kr4 qpf file in alt_e40_avalon_top_sv_kr4_13_1 directory 2 Re compiled the alt_e40_avalon_top_sv_kr4_13...

Page 10: ...Figure 6 Transceiver Bank...

Page 11: ...s Note that cables should be in orders of negative and positive Run the main_run tcl under system_console folder in system console and go to KR4_Status tab change KR4 Settings by reading and writing r...

Page 12: ...ust turn off for TX to RX loopback test 2 Force negotiated to FEC mode 3 Reset SEQ is the reset of initiate auto negotiate and link training function The KR4 status control panel needs to configure fi...

Page 13: ...vice setup register 0xB0 and 0xC0 don t need to change Only register 0xD0 needs to change to 0x82b85111 for long backplane System Monitor Panel The system monitor panel contains all the error message...

Page 14: ...re below Figure 11 System Control Panel Packet Monitor Panel This hardware demo design only able to generate randomize size packet Continually generate packet can be trigger by press Send Pkt button S...

Page 15: ...is one of the methods to confirm the test pass or fail If all TX counter are equal to RX counter that means pass Otherwise it could be a hardware issue Try to reconnect your cables replace cables or c...

Page 16: ...data To resolve the problem check pin assignments and try to use alternative pins in the same transceiver bank Quartus strictly requires TX RX to use compatible pins so user might need to try multiple...

Page 17: ...altera www global en_US pdfs literature ug ug_40_100gbe pdf Signal Integrity Development Kit Stratix V GT Edition Board https www altera com products boards_and_kits dev kits altera kit sv gt si html...