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Summary of Contents for AM-100

Page 1: ...JAN l 1979 r i Ipha rnlCra TECHNICAL MANUAL FOR AM OC 2 BOARD 1 B BIT CPU DWM 001 00 00 ...

Page 2: ... alpha rnICrD TECHNICAL MANUAL FOR AM DD 2 BOARD 1 6 BIT CPU Manufactured By ALPHA MICROSYSTEMS 17881 SKY PARK NORTH IRVINE CALIFORNIA 8271 4 ...

Page 3: ...on fidence and will not be copied or reproduced in whole or in part nor used or revealed to any person in any manner except to meet the purposes for which it was delivered Additional rights and obligations regarding this document and its contents may be de med by a separate written agreement with ALPHA MICRO SYSTEMS and if so suc1t separate written agreement shall be controlling AMOS Alpha BASIC a...

Page 4: ...NCE FROM NAME NOTE Use this form to communicate any errors ADDRESS suggested changes or general comments about this document If necessary call us at CITY 17141957 6076 STATE ZIP DOCUMENT COMMENTS TITLE NUMBER REVISION _ FOLD STAPLE MArl ZZF OOOO2 01 ...

Page 5: ... 1 I I 1 I 1 I I 1 1 I 1 1 I I 1 I 1 1 I l I Z o S u FOLD FOLD PLACE STAMP HERE alpha mlcro IIIIl 17881 Sky Park North r Ilne California 92714 ATTN EDUCATIONAL SERVICES DIVISION FOLO FOLD I I I 1 1 1 1 1 I 1 1 I I 1 1 1 I 1 I 1 I ...

Page 6: ...TA Introduction Capabilities and Specifications Interface Description and Wiring User Options Interrupt and DMA Options System Connections SECTION 3 PROGRA ING Introduction System Configuration Software Overview Operating System Assembly Language Program Text Editor Utility and Sort Programs A1phabasic Program Accounting Package A1phaLisp A1phaPasca1 i 1 1 1 1 1 2 2 1 2 1 2 2 2 6 2 8 2 8 3 1 3 1 3...

Page 7: ...2 4 Initialization and Status 4 47 4 2 5 Data Access 4 48 4 2 5 1 Addressing Operations 4 50 4 2 5 2 Write Operations 4 50 4 2 5 3 Read Operations 4 51 4 2 6 DMA and Interrupt Operations 4 51 4 2 6 1 CPU Chip Set Interrupts 4 52 4 2 6 2 Vectored Interrupts 4 53 4 2 6 3 DMA Operations 4 53 4 3 CPU Microprocessor Chip Set Description 4 54 4 3 1 System Components 4 58 4 3 1 1 Registers 4 59 4 3 1 2 I...

Page 8: ...ne to Three Line Encoder Board 2 U29 U30 Data Selector Multiplexer Board 1 U16 U17 U18 U21 NAND TTL to MOS Driver Board Board 1 U2 U3 D Positive Edge riggered Flip Flops with Preset and Clear Board 2 U6 U18 U19 U23 U31 U32 U34 U36 Paragraph 4 3 3 4 3 3 1 4 3 3 2 4 3 4 4 3 5 4 3 5 1 4 3 5 2 4 3 5 3 4 3 5 4 4 3 5 5 4 3 6 4 3 6 1 4 3 6 2 4 3 6 3 4 3 6 4 4 3 6 5 4 4 4 41 4 4 2 4 4 3 4 4 4 4 4 5 4 4 6 ...

Page 9: ...al Voltage Controlled Oscillators Board 2 US Decoder Board 2 U7 U8 U42 D Flip Flops With Clear Board 1 U13 U14 U25 Board 2 UlO Tri State Octal Buffers Board 1 U6 U11 4 153 4 154 4 155 4 156 4 157 U19 U27 4 158 5 0 5 1 5 2 SECTION 5 MAINTENANCE AND TROUBLESHOOTING Introduction Circuit Board Checkout Warranty Procedures SECTION 6 SCHEMATIC AND PARTS LIST 5 1 5 1 5 2 Schematic and Parts List iv 6 1 ...

Page 10: ...0 Bus DMA Timing CPU Chip Set Microinstruction Bus Timing AM lOO Functional Block Diagram AM lOO System Clocks Sequencer Flow Diagram Sequencer Logic Equations CPU Read Byte Timing CPU Read Word Timing CPU Write Byte Timing CPU Write Word Timing CPU Read Modify Write Byte Timing CPU Read Modify Write Word Timing AM lOO Power Up Sequence MCP 1600 Microprocessor Block Diagram Register File 01 Data P...

Page 11: ...te of Array No 3 Array No 4 Organization 01 Data Flow 2 Data Flow 3 Data Flow 4 Data Flow System Interconnections Microprocessor Set TTL Output Timing CP1631B Microinstruction Bus Interface Timing Control Chip Microinstruction Bus Timing Microinstruction Bus Timing CP1631B I O Instruction Condition Testing Execution of Read Instruction Execution of Write Instruction Execution of Input Instruction ...

Page 12: ...tate Buffer Connections Eight Line to Three Line Encoder Connections Data Selector Multiplexer Connections NAND TTL To MOS Driver Connections D Flip Flop Connections J K Flip Flop Connections One Shot Connections Dual Voltage Controlled Oscillator Connections Decoder Connections D Flip Flop Connections Tri State Octal Buffer Connections vii Page 4 144 4 145 4 146 4 147 4 148 4 149 4 150 4 151 4 15...

Page 13: ...us Interface Signals List AM I00 Signals List Microm State Code Functions Status Byte Buffer Bits CPU Chip Set Interrupts Data Chip CP1611B Pin Assignments Control Chip CP1621B Pin Assignments Microm Chip CP1631B Pin Assignments Translation State Code Outputs 4 of 7 Translation State Code Outputs 5 of 7 Microinstruction Set Microinstructions Summary of Microinstruction and Status Flags Microbus Ti...

Page 14: ...y 1 1 CIRCUIT BOARD DESCRIPTION The AM IOO CPU circuit board set is a 16 bit microprocessor board set that is compatible with the 5 100 Bus structure The AM IOO utilizes the Western Digital WD16 chip set microprogrammed to enhance the software of the operating system The microprocessor provides 16 bit flexibility and speed with floating point arithmetic to provide large throughput The two board AM...

Page 15: ...ompatible with many available peripherals from other manufacturers A block diagram of the system capability is contained in Figure 1 2 This shows the basic 5 100 Bus structure the currently avail able Alpha Micro circuit cards and the commercially available peripherals that can be used for a fully integrated system 1 2 t ...

Page 16: ... Rau E 0 0 0 l EAW HEAAI i g 0 I DRIVERS AVAILABLE 0 0 0 W O 0 gi i 0 a 0 Z 0 d a 0 o j 0 0 Zo oX 0 ACT V 0 0 o 1 O rPA DI 2 i i 00 AOOS REGENT 100 00 i i J 0 0 g Ii S LEAR SIEGLER AOM_1 o tomO AU LEAR SJEGL FI ADM 2 1 4 LEAR SJEGLER AOM 3 cae PHOENIX DATA MeOlA 1520 CAL COW CDC HAWK ORNE Dl IVE toM BYTE HAZELTINE 1l1lO 1RtOENT SERIES il427 H 10 M SYTE 0 2 TEXAS JNL SIL 700 FOIUlATTEA I TO FOUFl D...

Page 17: ... REI Y LOGIC lDSELECT oMA CONTROl LOGIC SEQUENCER HIS l Te 1 COMMAND I __ _ L J STATUS LOGIC I I I ADDRESS HEADER I 1 DA A llt ADDRESS I L T _ l 1 1 i 1 __ I STORAGE t ADDRESS LATON DATA IN 1 7 XDMAGRANT DATA ADDRESS DATA N OUT OATA r I 0 CONTROLS oMA CONTROLS Figure 1 1 AM IOO Simplified Block Diagram 1 3 1 4 Blank ...

Page 18: ... complete system Specifications for the AM lOO are contained in Table 2 1 Table 2 1 AM lOO Specifications PARAMETER SPECIFICATION Interface type Standard S lOO Bus l6 Bit words byte multiplexed for compatibility to 8 bit peripherals and memories Instruction Set Over 150 standard instructions coded in unique microcode executed on the WD 16 CPU chip set Arithmetic Hardware floating point arithmetic ...

Page 19: ...upt line count C Real Time Clock Standard Feature Circuit Boards Two board set standard 5 x 10 with lOO pin connectors 2 2 INTERFACE DESCRIPTION AND WIRING The AM lOa CPU interfaces with the standard S IOO Bus structure All data inputs outputs and control signals are transferred through these lines The S IOO bus con nections are made by the bottom edge connectors and are listed in Table 2 2 2 2 ...

Page 20: ...ss 3 31 A4 Address 4 30 AS Address S 29 A6 Address 6 82 A7 Address 7 83 A8 Address 8 84 A9 Address 9 34 AID Address 10 37 All Address 11 87 A12 Address 12 33 A13 Address 13 85 A14 Address 14 86 A15 Address 15 32 CLOC 2 MHz Clock 49 DID Data Input Bus 95 DII Bits 0 7 94 DI2 41 DI3 42 DI4 91 DIS 92 DI6 93 DI7 43 2 3 ...

Page 21: ...RI 62 DMAGR2 61 DMAGR3 60 DMAGR4 59 DMAGR5 58 DMAGR6 57 DMAGR7 56 DMARCVD DMA Received 64 DOO Data Out Bus 36 DOl Bits 0 7 35 DO 2 88 D03 89 D04 38 DOS 39 D06 40 DO 7 90 C CDSB Not Used t 18 ADDDSB 19 DODSB 22 I RITE emory lI ri te 68 PDBIN Data Bus In 78 PHLDA P Hold Acknowledge 26 2 4 ...

Page 22: ...E CPU Interrupt Enable 28 POC Power On Clear 99 PRESET Preset 75 PSYNC Processor Sync 76 PWAIT CPU Wait 27 PWR Write Strobe 77 SINP I O Input Cycle 46 SINTA Interrupt Acknowledge 96 SMEMR Memory Read Cycle 47 SMI Bus Master OP Code Fetch 44 SOUT I O Output Cycle 45 SWO Bus Master Output 97 2 5 ...

Page 23: ...f the optional capabilities of the AM lOa CPU are exercised with software and an overview of the available software capability is contained in Section 3 The hardware option that must be implemented is for the bootstrap Loader program and determines which peripheral the boot loader is accessed from The boot loader may be accessed from either the AM 200 circuit board floppy disk controller the AM 50...

Page 24: ...that are jumper selectable are A8 A13 with A14 and AlS always high 1 To select an address pins 3 4 S 6 7 and 8 can be jumpered to ground or left open to generate the desired code An open no jumper selects a one for that address bit and a jump r to pin 14 selects a zero Pins 9 U3 must NOTE 10 11 12 13 and 14 on header always be connected together that correspond to the various address bits The pins...

Page 25: ... CONNECTIONS The AM lOO board set plugs into two adjacent slots in a 5 100 Bus chassis and are connected together by a 40 pin flat cable along the top of the circuit boards An additional input must be connected to the real time clock of the CPU This can be supplied from the 50 or 60 Hz power of the low voltage power supply in the S IOO bus chassis Connect this 50 or 60 Hz signal to CPU board 2 at ...

Page 26: ...e transformer tap connection located in Step 2 Make sure that the cable is long enough to be conveniently routed 5 Solder the cut end of the cable to the transformer tap connection 6 Before attaching the cable to the AM IOO perform the following steps a Plug in the chassis and turn on AC power b Observe the waveform at the E Z hook contact It should appear as a 10 volt signal at 60 or 50 Hz 7 If t...

Page 27: ... I I I o R5 I I c I R I I 0 J o c lOA I 0 t IV lC f I I L I I I I I I I 0 I t R4ao 1 I t I CZ w 10 I I t ____ 10 I I I I cRi CRZ F 0 I I I c l Jib I I I t c e A I I w I I I I I I I I I c _ q I I I 10 I I I I caD 0 6 Go 1 5 o M 10T I 1 i J T IO t I I II c J I OHa I 1 1 1 I e_run I_ _ __ l TO A N 321 N o a Figure 2 2 Real Time Clock Connection j ...

Page 28: ...disk subsystem AM 200 AM ZlO Z Ten megabyte hard disk AM SOO 3 Large storage capacity hard disk AM 400 AM 410 4 Tape storage subsystem AM 600 To utilize other devices in the system it is necessary to write a driver program for the device and place the resulting module in a preassigned disk area The bootstrap PROM can be located on either the floppy controller interface board AM 200 or the hard dis...

Page 29: ... 1 port memory bd 50 6F Unassigned 70 7F Phone Link DC Hayes bd 80 83 Imsai PIO parallel port Data I O control etc 84 9F Unassigned AD A7 AM 600 Mag Tape I F A8 AF Unassigned BO BF AM 3l0 4 Port Communications Bd 4 ports required bd CO C7 ICOM Floppy Controller or AM 500 Disk Controller 4 ports bd C8 CF Unassigned C2 Unassigned 3 2 ...

Page 30: ...matter I F E8 EF AM 300 Alternate Znd board FO F7 AM ZOO Floppy Controller or AM 210 Floppy Controller F8 FF AM 300 6 Port Serial I O Board Table 3 Z Boot Addresses Address Hex Boot Location F400 AM SOO Boot Address AM 410 Boot Address FCOO AM ZOO Boot Address AM ZIO Boot Address AM 400 Boot address CODa ICOM Floppy Boot Address 3 3 ...

Page 31: ... AM 600 Mag Tape Controller 6 AM 200 Floppy Controller 7 Table 3 4 Interrupt Levels Level Device 0 I AM 310 4 Port Communications Board 2 AM 410 Disk Controller 3 AM 300 6 Port Serial I O 4 AM SOO Disk Controller Not available on old systems 7 3 4 ...

Page 32: ...ontrol several terminals The status of each job may be optionally displayed on a central video display interfaced through a controller The I O structure is fully device independent and contained within the monitor To incorporate a new device into the system the user creates a software driver to interface to the device and includes it in the monitor The terminal service routines are also device ind...

Page 33: ...ystem status monitor programs 7 A system generation procedure that allows custom tailoring of the monitor to individual user requirements 8 Text formatting 3 2 5 ALPHABASIC PROGRAM The AlphaBasic programming language processor is a full com piler that is disk oriented and supports 1 3 4 5 6 Strings Hulti dimensioned arrays Disk I O file accessing A unique variable mapping system for file manipula ...

Page 34: ... these is a fully interactive menu driven complete system by itself However interface is provided between all five modules to create a totally integrated accounting package 3 2 7 ALPHALISP An Alpha Micro version of the programming language LISP is available It is designed for users that require a language that is both a formal mathematical language and with extensions a convenient programming lang...

Page 35: ......

Page 36: ...support the CPU chip set 4 1 CPU CONFIGRUATION The AM lOO circuit cards function as a l6 bit CPU that plugs in to an S IOO Bus system The data processing logic is contained on a two board set that is fUlly integrated into an S IOO Bus system 4 1 1 AM lOO TWO BOARD SET The AM lOO CPU is packaged on two circuit boards connected together by a 40 conductor flat ribbon cable Both boards mate with the s...

Page 37: ...atus and utility lines There are also eight lines for vectored interrupts DMA requests and eight for DMA Grant lines The various devices connected to the bus are referred to as bus master and bus slave depending on the opera tional configuration taking place The CPU is not the only device that can control the bus Any DMA device has the capa bility of controlling the bus as a bus master The command...

Page 38: ...Line Table 4 2 S IOO Bus Status Lines SIGNAL NAME SMI Bus Master OP Code Fetch SOUT I O Output Cycle SINP I O Input Cycle SMEMR Memory Read Cycle SWO Bus Master Output SINTA Interrupt Acknowledge Table 4 3 S lOO Bus Utility Lines SIGNAL NAME Power GND 8VDC 16VDC 16VDC 02 2 MHz Phase 2 Clock CLOC 2 MHz Clock MWRITE Memory Write PRESET Preset POC Power On Clear 4 3 ...

Page 39: ...he timing of the signals involved with a WRITE BYTE sequence on the S lOO bus is shown in Figure 4 2 With this sequence PSYNC starts the bus cycle like the read timing Signal PWR occurs next to indicate that there is valid data on the bus that is to be written into the addressed location Status and address data is placed on the bus 100 nsec after PSYNC by the bus master The WRITE WORD cycle is a s...

Page 40: ... nL _ READ WORD TIMING DATA READ PDBIN PSYNC r 1 _ _ JI L J 1 _ 100 NS j rffi 100 NS 1 nOO NS I j I r lOO NS LOW BYTE I HI BYTE _ aOO NS I _l aOO NS I STATUS ADDR PDBIN MAY BE STRETCHED BY CONTROLLING PRDY PRDY IS EXAMINED AT PI tWD LEADING EDGE TIME DURING PDBIN Figure 4 L S IOO Bus Read Timing 4 5 ...

Page 41: ...1 100 NS 1 I 1 I 00 NS r OONS 00 NS I OONS LOW BYTE HIGH BYTE 1 LOW BYTE HIGH BYTE DATA PSYNC r 1 r 1 _ _I ffiL_ _ 1 _ STATUS ADDR PSYNC MAY BE STRETCHED ONE DR MORE CYCLES DUE TO DOUT DELAY CAUSED BY MICROCODE ilWR MAY B STRETCHED BY CONTROLLI G PRDY PRDY IS EXAMINED AT 4 1 IWDI LEADING EDGE TIME DURlNG PWR Figure 4 2 5 100 Write Timing 4 6 ...

Page 42: ... I 100NS 1 1 I I 200 NS _I I I I 400NS In x LOW BYTE sSYTEt OONSr a00 NS I k 1100NS QO N I 1 1 1 1 PDBIN PSYNC r l I _ _I L I ___ ill DATA READ OUT STATUS AD DR LOW BYTE __ H G H B Y_T E __ LOW BYTE UGH GYTE PSYNC MAY BE STRETCHED ONE OR MORE CYCLES DUE TO DOUT DELAY CAUSED BY MICROCODE illPDBIN AND j5W l f MAY BE STRETCHED BY CONTROLLING PRDY PRDY IS EXAMINED AT P1 IWDI LEADING EDGE TIME DURING P...

Page 43: ... CPU I 55 BUSSES TRiSTATE I 100 NS DMARCVD 1 2 WD 8 DMAGRANTX MAY BE DELAYED IF A BUS CYCLE IS IN PROGRESS WHEN A DMA REQUEST IS GENERATED IT WILL BE ISSUED IMMEDIATELY FOLLOWING THE COMPLETION OF SYNC 2 PHOtO IS ALWAYS FORCED LOW 3 PHLDA IS ALWAYS HIGH Figure 4 4 5 100 Bus DMA Timing 4 8 ...

Page 44: ...in the AM lOO system refer to Table 4 4 This table lists all signals in alphabetical order with AM IOO pin numbers and also the sheet number of the schematic where they interface with the AM lOO CPU A complete description of each signal is also given 4 9 ...

Page 45: ...Ul 9 A3 Address 3 31 CPUl 9 A4 Address 4 30 CPUl 9 AS Address 5 29 CPUl 9 A6 Address 6 82 CPUl 9 A7 Address 7 83 CPUl 9 A8 Address 8 84 CPU1 l0 A9 Address 9 34 CPU1 l0 AID Address 10 37 CPU1 l0 All Address 11 87 CPU1 10 A12 Address 12 33 CPU1 10 A13 Address 13 85 CPU1 l0 A14 Address 14 86 CPU1 10 A15 Address 15 32 CPUI 10 CLOC 2 MHz Clock 49 r PU2 3 2 lliz clock from same source as 2 I ...

Page 46: ...it tri state data bus from bus slave to bus master DMAGRO IDMA Grant DMAGR1 DMAGR2 DMAGR3 DMAGR4 DMAGR5 DMAGR6 DMAGR7 DMARCVDIDMA Received 63 62 61 60 59 58 57 56 64 CPUZ 5 CPU2 5 CPU2 5 CPU2 5 CPU2 5 CPU2 5 CPU2 5 CPU2 5 CPU2 5 Grant signal issued to the highest priority controller that has requested the bus CPU response to DMA request indicating that a DMA exchange is in process No other DMA con...

Page 47: ... 3 DOS 39 CPUl 8 D06 I 40 CPUl 8 DO 90 CPUl 8 ENDF 18 CPU2 2 Only used internal to the AM IOO 19 22 MWRITE l Iemory Write 68 CPU2 2 Gated combination of PWR and SOUTo PDBIN Data Bus In 78 CPU2 9 Read Enable Used by bus master to request address slave to place data on the data bus PHLDA P Hold 26 CPU2 3 When asserted indicates that the CPU is releasing control of the bus in response to a DMA reques...

Page 48: ...nable not used by Alpha Micro Systems POC Power On Clear 99 CPU2 3 Clear signal generated by the CPU on initial turn an PRESET Preset 75 CPU2 2 Reset signal normally originating from front panel reset pushbutton PSYNC Processor Sync 76 CPU2 7 When asserted indicates the start of a bus cycle PWAIT CPU Wait 27 CPU2 7 When asserted indicates that the CPU is in a wait period PWR Write Strobe 77 CPU2 7...

Page 49: ...r of an interrupt request SMEMR M mory Read Cycle 47 CPU2 7 When asserted indicates that the current bus cycle is a bus master input from a memory address SMl Bus Master 44 CPU2 7 When asserted indicates that the current bus OP Code Fetch cycle is a bus master OP code fetch SOUT I O Output Cycle 45 CPU2 7 When asserted indicates that the current bus cycle is a bus master output to an I O address S...

Page 50: ... VB Vectored Interrupt 3 7 CPU2 5 VI4 Vectored Interrupt 4 8 CPU2 5 VI5 Vectored Interrupt 5 9 CPU2 5 VI6 Vectored Interrupt 6 10 CPU2 5 VI7 Vectored Interrupt 7 11 CPU2 6 STVAL Status Valid 25 CPU2 3 Indicates Status Address lines valid during PSYNC 2 Phase 2 Clock 24 CPU2 3 2 MHz clock Phase 2 Master Timing signal for the bus 8V 8vdc power 1 51 CPU1 l System power and ground 1 51 CPU2 1 16V 16 v...

Page 51: ...are as follows a 16 bit architecture with both word and byte operation b l6 bit data access port to memory and I O c Eight l6 bitregisters d Four external interrupts e Three internal interrupts f Eight addressing modes The chip set is microprogrammable by the coded data within the microms Figure 4 5 contains a block diagram of the five chips in the CPU chip set 4 1 3 1 DATA CHIP The data chip prov...

Page 52: ...11 4 U30 MIBO MIB15 CH tP SELECT TO STATE CODE DECODER 512 22 MICRDM CHIP NO 2 CP 1631 29 U31 CHIP SELECT 512 22 MICROM CHIP NO 3 CP 1631 30 1 U32 COMPUTE CONTROL CHIP DATA CHIP DALO DAL15 CP1B618 CP 1611 8 RESET U28 U29 10 13 WAIT RPLY BUSY SYNC DIN DOUT we lACK Figure 4 5 CPU Chip set 4 17 ...

Page 53: ...ctions and the two control bits form a high impedance tri state bus Bits MIB18 MIB2l are the auxiliary bits and are the state codes that direct external logic to perform special functions 4 1 3 4 MICROINSTRUCTION BUS The Microinstruction Bus MIB is a high impedance MOS bus for data transmission between the chips in the CPU and is very sensitive to external monitoring even with oscilloscope probes ...

Page 54: ... bits 0 10 This address data comes from the control c ip Phase three decodes the microinstruction Phase four provides the precharge necessary for the nodes since this is a MOS bus At phase 1 the microinstruction is placed on the bus and the proces s repeats The function of the state codes and operation of the CPU with its associated external logic is described in paragraph 4 2 4 19 ...

Page 55: ... 1 PLACED INSTRUCTION DURING 9 1 ON BUS IS ACCESSED DURING 9 2 Except for MIB15 which is precharged at 03 It is used to transfer conditional jump results back to the control chip during 04 MIB16 is precharged during 02 and 04 It is conditionally discharged during 01 to control RR register and conditionally discharged during 03 to disable microm output buffers Figure 4 6 Microinstruction Bus Timing...

Page 56: ...hip set with its associated logic elements An overall blQck diagram of the CPU board set is shown in Figure 4 7 Sheet 1 contains all the logic on CPU board 1 and sheet 2 contains all the logic on board 2 Table 4 5 contains a complete list of the signals in the AM lOO CPU The list is alphabetical by signal mnemonic and a description is given for the function of each signal and the location where it...

Page 57: ......

Page 58: ...FERS HEADER U6 AL07 U A R r oU6 DAL04 12FF 12FF DAL OAL7 DALB Y L DAL15 D N OE eLK READY I LOW3YTE E r INPUT STORAGE AL7 HIBYTE U9 U1Q rHIBYTE VINTR1NINTR3 lOIN 27 D1O Q17 OAUl DAU5 INTERRUPT A i i lS L STORAGE UJ D DiN DATA XOMAGRANT l DIN X DMAG Yll BDALO aOAL7 I DATA SELECT I J V BOALS OOC Dl L BDAU5 Ul7 U18 fHIBYTE AD m RA01 AA07 Al A7 ADDRESS HeN D U13 U14 ADDRESS r U RAOB RA15 SELECT A8 A15 ...

Page 59: ...g VECTORED L INl ERAUf TS HIBYTE WBFF m XROY PRDY SEQUENCER u PDRIN U20 U28 U40 0 U50 USl U roUT HIBYTE READY IAO I L RAO COUT i HREE FOUR FIVE SEVEN REST RMW SC2 roUT L MWRITE W 112B 0BiN MSYNC1 MSYiiC3 R sEL I w I w COMMAJI O 1i IO EL looEl AND STATUS 1 LOG C OSEe U25 U28 CONTAOll r J u U33 U34 SYNC WAIT om lACK lACK U SWO SM1 SIN lSTATUSI SMEMR SINTA HI XDMAGRANT DMARCVD fiiiEffi PR E Sffi OM M...

Page 60: ... CPUl 4 Tri state bus for Data and Address Lines DALIS 6 7 DBIN Data Bus In 2 CPU2 8 Read Enable equivalent to PDBIN on 100 Bus DBIN Enables CPU to read data from the Data In Bus DIN Data In 1 5 CPUl 5 Control signal from the processor to cause the DIN 2 CPU2 6 address unit to gate its read data on the data lines DOUT Data Out 2 9 CPU1 S Control signal from the processor which is made high CPU2 3 ...

Page 61: ... asse rted switches the upper byte bits 8 15 HIBYTE CPU2 8 to the output port from the WD16 When it is low the lower byte bits 0 7 is selected lACK Interrupt 2 7 CPUl S Control signal output from the CPU to indicate that lACK Acknowledge CPU2 7 the processor is responding to an interrupt lAO luitiate Address 1 26 CPUI IO Sequencer output to generate LSB of address byte AD CPUZ 3 in either bit AD o...

Page 62: ...by any 2 CPUZ 6 vectored interrupt JFlVE Set Sequence 5 2 CPUZ 9 J input to sequencer flip flop 5 JFOUR Set Sequence 4 2 CPUZ 9 J input to sequencer flip flop 4 JFOUR JREST Set Sequence Rest 2 CPUZ 8 J input to sequencer flip flop zero REST JSEVEN Set Sequence 7 2 CPUZ 9 J input to sequencer flip flop 7 JTHREE Set Sequence 3 2 CPUZ 9 J input to sequencer flip flop 3 MIBOO Microinstruction 1 ZI 22 ...

Page 63: ... Stored Address Zero I 27 CPUl 9 Address data bit zero stored from the DAL bus clocked 2 CPU2 3 into the register by SYNC RAOI Stored Address I CFUl 9 Address Data stored from the DAL bus clocked into RAIS the register by SYNC Rl Read Byte 2 CPUZ 4 State Code decoder signal for Read Byte 0Feration RB READI iORD Read Word 2 CPU2 4 State code decoder signal for Read Word operation READY Ready 1 4 CP...

Page 64: ...ressed unit to respond Z CPU2 6 to the processors data access signals J 5T CPU Reset 1 15 CPUl S Resets CPU chip set on initial power up 2 CPlJ2 6 RTC Real Time Clock Z CPU2 2 RTCFF CPU Real Time Clock 1 12 CPUl S Real time clock input to CPU 2 CPU2 6 SCI SCF State Codes 1 F Hex 2 CPU2 4 Outputs of state code decoder SEVEN Sequencer Count Seven 2 CPU2 9 Sequencer output for count seven SIX Sequenc...

Page 65: ...7 Indicates that the current process is a wri te NO operation WAIT Wait 1 CPUI 4 Signal from CPU data chip to control chip to establish whether the data chip is in the Run or Wait mode Low Run and the microinstruction is loaded and executed WB Wri te Byte 1 8 CPUI 5 Control signal from the processor which is high when 2 CPUZ 3 the address is on the bus to signify a WRITE rather than a READ and hig...

Page 66: ...4 8 2 CPU2 2 2B Phase 2 Clock 2 CPU2 8 Phase 2 of 2 ffiz 4 phase clock buffered for operation sequencer flip flops fl2M Phase 2 Clock 1 CPUl 1 Phase 2 of 2 MHz 4 phase clock buffered for 10 5 volt MOS Levels operation of CPU chi p set 03 Phase 3 clock 1 20 CPUl l Phase 3 of 2 MHz 4 phase clock see Figure 4 8 2 CFU2 2 3M Phase 3 Clock 1 CPUI l Phase 3 of 2 MHz 4 phase clock buffered for operation M...

Page 67: ...or provides the internal clock signals to drive the CPU chip set and to synchronize its associated logic Operation of U12 is described in paragraph 4 4 1 The timing relationship of the 5 100 bus clocks and the four phase clocks is described in Figure 4 8 The TTL level clocks from CPU 2 are sent to CPU 1 where they are buffered through U2 and U3 to a level of at least 10 5 volts to drive the CPU ch...

Page 68: ...read modify write The state codes and their functions are listed in Table 4 6 4 2 3 SEQUENCER OPERATION The sequencer on the AM IOO CPU provides the timing and syn chronizing required to interface the 16 bit CPU chip set to the 8 bit S 100 Bus There are ten states in this sequencer that provide the various operations required for CPU data pro cessing Function for memory or I O Once around for byte...

Page 69: ...s the interrupt enable line 12 Resets 12 flip flop 0110 ESRR External Status Register Generated during an INPUT STATUS BYTE micro op code to indicate that Request the external status register is being requested 0111 SRS System Reset Not used 1000 BYTE Read Byte Operation Generated during an INPUT BYTE micro op code to indicate a read byte operation without a read modify write Not llsed on AM IOO 1...

Page 70: ...terrupt 1100 EARR External Address Controls where the CPU looks for the bootstrap PROM upon po er up Register Request 1101 Duplicate of BYTE Same as BYTE except one bit sooner 1110 Duplicate of RMWW Same as RMWW except one bit seener 1111 Duplicate of RMWB Same as RMWB except one bit sooner 4 37 ...

Page 71: ...ssary to produce the bus signals drawn underneath Only one state of the sequencer is active at a time On initial power up the reset line PRESETB is forced low initializing the sequencer to the rest or zero state The sequencer is in this state until a bus operation is required When the CPU chip set is ready for an I O operation SYNC is asserted to generate MSYNCI which is state one of the sequencer...

Page 72: ... I I K L 1J r J I 1 1 J REST RES EST READY K PSYNC SEOUENCE OF OPERATION Q2 REPLY LOIlIC 1 READY BYTE tMEM OR 1101 0 102 11 READY RIl DIN 2 READY WORD lMEM OR 1101 0 102 3 2 11 READY RW HYIlITE DIN 3 WRITE IlYTE IMEM OR 1101 0 1440 READY WB 5 4 WRITE WORD lMEM OR 1101 0 1_7440 READY WB 5 HIBYTE 5 RMW BYTE lMEMI 0 102 H3 ABOVE 6 RWM WORD IMEMI 0 1 2 3 2 7 e o 2M ABOVE 7 RMWBYTE 11I01 0 1 DIN 3 ABOV...

Page 73: ...T K4 7 K5 J6 3 J3 READY HIBYTE DBIN RB RMWB K3 3 6 J6 5 READY K6 JREST J7 7 J7 6 WBFF HIBYTE K7 7 ADDRESS lSB LOGIC Ao Aol READWORD Ws DOUT HIBYTE READWORD Ws DOUT HIBYTE JHIBVTE J3 J7 KHIBYTE J4 DIR RESET REST READY JREADY PRDY XRDY DBIN 5 KREADY PSYNC 6 DIR RESET REST BUS SIGNALS PSYNC MSYNCl 4 7 3 PWR 5 PDBIN DBIN SMEMR IOWEl SWo S NP IOSEl sw SOUT IOSEl SWo MWR ITE PWR SOOi Figure 4 10 Sequenc...

Page 74: ...ONS 4 8 1 C OONS ST TUS ADOR 1 eOO NS i DATA RE D In _ 2 WDI 11 1 READY 11 1 11 _ RPLY 21 JIl _ READ BYTE MEMORY OR I O 8 PDBIN MAY BE STRETCHED BY CONTROLLING PRDY PRDY IS EXAMINED AT llWD LEADING EDGE TIME DURING PDBIN Figure 4 11 CPU Read Byte Timing 4 41 ...

Page 75: ...PDBIN MAY BE STRETCHED BY CONTROLLING PRDY PRDY IS EXAMINED AT IPI IWD LEADING EDGE TIME DURING PDBIN IP21WDI SYNC IIP2l _ DIN IIP2 READY IIPIi Il J RPLY IIP2 I 1 _ 1 _ READY WORD 1MEMORY PDBIN MAY BE STRETCHED BY CONTROLLING PRDY PRDY IS EXAMINED AT IPI IWD LEADING EDGE TIME DURING PDBIN Figure 4 12 CPU Read Word Timing 4 42 ...

Page 76: ... IP21 I DOUT I IP II_ _ 1 READY IPI r 1 1 1 _ RPLY IIP 2 1 11 _ WAITE BYTE MEMORY OR 1 01 PSYNC MAY BE STRETCHED ONE OR MORE CYCLES DUE TO DOUT DELAY CAUSED BY MICROCODE PWR MAY BE STRETCHED BY CONTROLLING PRDY PRDY IS EXAMINED AT I IWDI LEADING EDGE TIME DURING PWR Figure 4 13 CPU Write Byte Timing 4 43 ...

Page 77: ...L J 1 1 1 _ STATUS ADDR P2 WD _ _ J SYNC I P 2 1_ _ DOUT P READY 1 P lI ___Jn Jr_l _ RPLY I P 21 _ _ I1 WRITE WORD MEMORY PSYNC MAY BE STRETCHED ONE OR MORE CYCLES DUE TO DDUT DELAY CAUSED BY MICROCODE 11 PWR MAY BE STRETCHED BY CONTROLLING PRDY PRDY IS EXAMINED AT P WD LEADING EDGE TIME DURING PWR Figure 4 14 CPU Write Word Timing 4 44 ...

Page 78: ... tP2 fWD SYNC ltP 2 _ DIN ltP 2 _ I I I I I I I I DOUT tP 1 J RPLY ltP 2 _ READY tP _ READoWRITE MODIFYoWRITE BYTE PSYNC MAY BE STRETCHED ONE OR MORE CYCLES DUE TO DOUT DELAY CAUSED BY MICROCODE PDBIN AND PWR MAY BE STRETCHED BY CONTROLLING PRDY PRDY IS EXAMINED AT tPl IWDI LEADING EDGE TIME DURING PDBIN OR I WR Figure 4 15 CPU Read Modify Write Byte Timing 4 45 ...

Page 79: ...S ADDR 1 OW BYTE I H_ G_H_B_Y_T_E __ OW BYTE HIGH BYTE 1 2 WDI L SYNC 1 21 DIN 1 21 L DoUT 11 1 READY 1 11 RP Y 1 21 READ MoDIFY WRITE WORD 1 PSYNC MAY BE STRETCHED ONE OR MORE CYC ES DUE TO DoUT DE AY CAUSED BY MICROCODE 1 PDBIN AND iiWR MAY BE STRETCHED BY CoNTRo INGPRDY PRDY IS EXAMINED AT 1 1 WD LEADING EDGE TIME DURING PDBIN OR PWR Figure 4 16 CPU Read Modify Write Word Timing 4 46 ...

Page 80: ...sists of two buffers the status Byte Register buffer and the External Address Register Select buffer The Status Byte buffer is used by the CPU chip set during power up to determine the initialization sequence There are eight bits in this register that function as defined in Table 4 7 The CPU chip set checks these bits as it proceeds through its initialization Table 4 7 Status Byte Buffer Bits BIT ...

Page 81: ...ap load program and begin executing When the RESET pushbutton is pressed the CPU sends out an external request to read the Status Register This signal is ISR that accesses the eight bits of data as defined in Table 4 7 The CPU then checks each bit as described in Figure 4 17 When the CPU has checked the eight bits of the Status Register signal EARS is asserted from the state code decoder and reads...

Page 82: ...RED TOOND RESET READ EXTERNAL STATUS NO NO OUTPUT SYSTeM RESET STALL 300 CYCLES CHECK BITS 0 1 READ EXTERNAL ADDRESS RGSiR OETERMINE SOOTSTRAP BASE ADDRESS MICROINSTRUCTION ADDRESs 0001 0002 0039 006 0071 0076 0081 0085 0189 I Figure 4 17 AM 100 Power Up Sequence 4 49 ...

Page 83: ...dress FFXX This generates signal IOSEL from the gate on U15 to distinguish between I O and memory operations Signal IOSEL switches the Data Select MUX to place AO A on both the upper and lower bytes of the address bus Address line AO is generated by the sequencer logic on CPU2 to provide for byte word data operations With word operations two sequential addresses are fetched so AO is sequenced firs...

Page 84: ...storage Signal READY from the sequencer indicates that the CPU chip set is ready to accept the data so it is clocked into the Low Byte Input Storage register The lower byte of data is on both DALO DAL7 and DAL8 DALlS and the CPU can read from either one For the read word sequence the lower byte is transmitted exactly like the read byte sequence The sequencer then starts another cycle and increment...

Page 85: ...U2 when any of the eight vectored interrupts have been asserted This signal is generated by decoder U29 inverted and stored in a D flip flop on UIO Interrupt II is the non vectored interrupt and the real time clock signal RTCFF supplies this input Interrupt 12 is an enable for 10 and II and is supplied by the user state codes This is generated by flip flop U18 on CPUZ that is preset by SC4 and cle...

Page 86: ...he interrupt storage register UI where they are clocked in by lACK When Data In DIN is received from the CPU lDIN is asserted which applies VlNTRI VINTR3 to the data bus DAL1 DAL3 The CPU then reads the interrupts from the bus 4 2 6 3 DMA OPERATIONS The AM IOO provides seven levels of DMA capability Levels VIO VI6 are jumper selectable and level 7 is wired directly to PHOLD The other DMA inputs ar...

Page 87: ...as memory and I O The list below describes the pertinent aspects of the set 8 bit Internal Organization l6 bit Data Access Port to Memory and I O 26 Registers Extensive Microinstruction Set Including Decimal Operations Single and Double Byte Operations Micro and Macro Level Condition Flags 512 Word x 22 bit Control ROM Control ROM Expandable to 2048 words Micro Level Subroutine Capability Programm...

Page 88: ...t may be expanded up to four MICROMs giving the user a total of 2 048 22 bit microinstructions In addition to the three parts comprising the Microprocessor Set twelve other available standard TTL parts are required These parts serve to Generate the clocks Latch and gate input signals Latch and gate output signals i i i r U rm m m 512 X 22 ADM CHIP CP1631B f cs I t 30 1 4 I I t TE TTL CONTROL DATA ...

Page 89: ...nts PIN PIN PIN PIN NO SIGNAL NO SIGNAL NO SIGNAL NO SIGNAL 1 03 11 DAL08 21 02 31 MIB07 2 VBB 12 DAL09 22 WAIT 32 MIB06 3 DAL00 13 DAL10 23 MIB15 33 MIB05 4 DAL01 14 DAL11 24 MIB14 34 MIB04 5 DAL02 15 DAL12 25 MIB13 35 MIB03 6 DAL03 16 DAL13 26 MIB12 36 MIB02 7 DAL04 17 DAL14 27 MIEll 37 MIB01 8 DAL05 18 DAL15 28 MIB10 38 MIB00 9 DAL06 19 VSS 29 MIB 09 39 VDD 10 DAL07 20 04 30 MIB08 40 01 4 56 ...

Page 90: ...IB01 8 BUSY 18 DIN 28 MIBl 38 MIB i l 9 COMPUTE 19 VSS 29 MIB09 39 VDD 10 RESET 20 f l4 30 MIB 8 40 1 Table 4 11 Microm Chip CPI631B Pin Assignments PIN PIN PIN PIN NO SIGNAL NO SIGNAL NO SIGNAL NO SIGNAL 1 3 11 MIB16 21 2 31 MIB 6 2 VBB 12 MIB17 22 VCC 32 MIB05 3 NC 13 MIB18 23 CHIP SELECT 33 MIB04 4 NC 14 MIB19 24 NC 34 MIB03 5 NC 15 MIB2 25 NC 35 MIB 2 6 NC 16 MIB21 26 MIB11 36 NC 7 MIB15 17 NC...

Page 91: ...three types of devices together and provides a path for the microinstructions to flow from the microinstruction ROM to both the Control and the Data Chip 5 Data Access Bus This bus provides access from the MCP1600 microprocessor set to the outside world Lines comprising this data access bus come from all three of the chip types Lines containing the address and data come from the Data Chip control ...

Page 92: ...p that describes the currently accessed linked consecutive pair of registers in the register file Note that when the G register is being used access to the register file is from the top down This is opposed to the access to the register file when only the A and B fields are being used as designators in which case it is from the bottom up This register is loaded by IW and LGL instructions Input Wor...

Page 93: ...l be from R 7 The other operand B Port will be from G l Assume G b a 1 b Then one operand A Port will be from G D The other operand B Port will be from R D Assume G 3 a 6 b A Then one operand A Port will be from R 6 The other operand B Port will be from R A Assume G 5 a 0 b 1 Then one operand A Port will be from G S The other operand B Port will be from G 6 4 60 ...

Page 94: ...of each 8 bit operation The ZB and NB bits are updated after every ALU operation C4 and C8 are updated only during Arithmetic or Shift operations These bits may be tested by Jump but their primary function is to pass result data from the first cycle of a word instruction to the second cycle The available status bits are ZB Set if the result of a Byte or Word operation is zero cleared otherwise NB ...

Page 95: ...e previous ALU results The updating of these flags can be selectively enabled or disabled at the discretion of the microprogrammer The condition flags are updated with odd numbered instruction opcodes in the range of 80 EF Z Flag Set if the result of a Byte or Word operation is zero cleared otherwise N Flag Set if the high order bit of the result of Byte or Word operation except for SRW and SRWC i...

Page 96: ...other flags are updated V Flag Set if there is an arithmetic overflow on Arithmetic operations cleared if there is no overflow and on Non arithmetic operations On Add operations overflow occurs when the sign of the two operands are the same and the sign of the result is different On Subtract operations overflow occurs when the signs of the two operands are different and the sign of the result is d...

Page 97: ...ach access of a microinstruction The LC can be altered by other than one through execution of a Jump instruction or a Return from Sub routine RFS instruc tion or by the invocation of a PTA translation Return Register The Return Register RR holds an 11 bit address and permits a subroutine depth of one in the micro program When a subroutine jump is indicated MIB 16 1 the return register stores the i...

Page 98: ...oper microinstruction data from the microinstruction ROM chip to both the control chip and the data chip These lines may also carry data between the data chip and the control chip under certain conditions MIB 16 controls the subroutine jump operation When MIB16 is set on a jump instruction it causes the incremented con tents of the LC register to be placed into the Return Register MIB17 if set cau...

Page 99: ...sy line With these lines the MCP1600 can control a wide variety of peripheral devices 4 3 1 5 MICROINSTRUCTION STORAGE The microinstruction ROM MICROM is a 512 x 22 bit word high speed ROM which stores the instructions of the micro program The transfer of addresses into the chip and the microinstruction out of the chip are performed over the MIB Address is received from push pull drivers in the Co...

Page 100: ...e presently fetched microinstruction the Control Chip is performing a transformation upon the presently executing macroinstruction to determine the address from which to fetch the next microinstruction to be executed The description of the processor proceeds by first outlining the operation of the Data Chip CPU and then in the following section outlining the operation of th Control Chip It is impo...

Page 101: ...control function decodes the C field and generates signals which control the gating of data to the various functions of the Data Chip In 02 the address decoder is interpreting the contents of A field and the B field and accessing the appropriate register in the register file Also during 02 the condition codes reflecting the result of the last ALU operation become valid They are presented to the FL...

Page 102: ...conditions are met and if JXX is asserted then MIBlS will cause the Control Chip to effect a jump on the next clock cycle As the next 01 clock occurs to start the next cycle of the instruction execution the data that was presented to the gating structure that controls access to the A input port of th register file is gated or not gated depending upon a signal from the Master Control into the regis...

Page 103: ...AGSL 0 oy if u 0 ltU w U 0 w tJ a f MU MV L O3 if03 4 B PORT A PORT 26 8 CONTROL LINES f FILE ASTER CO JTROL ADDRESS OEcODER O2 1 L 4 1 8 a t 3 t MIA A r 8 C OF 101 G rr 1 I i WAIT _ JXX Figure 4 20 iiJI Data Paths 4 70 ...

Page 104: ...9 Y FL AGS I Q U Q I I U w u 1 Q r MU I MU I I y L 3 B PORT A PORT 26 8 CONTROL LINES FILE I I ASTER C TROL ADDRESS DECODER 2 t L 4 f 8 8 3 r L MIR A B C p 101 G I k tQ i WAIT tmm _ JXX Figure 4 21 2 Data Paths 4 71 ...

Page 105: ...u w 0 99 u a Il1J w u 0 w 1 C1 I MU I MU I t I I 3 I i 3 e PQRT A PORT 26 8 CONTROL LINES f FILE 01 ASTER CO HRQL ADDRESS DECODER 1 L I t _ t 3 r MIR A B C GPO j01 G r J I ir J WAIT l JXX Figure 4 22 03 Data Paths 4 72 ...

Page 106: ... w o 4 Fl AGS 1 u 0 AlIJ w U 1 w I MU I MU L L t If m B PORT A PORT 26 y B CONTROL LINES FILE I VASTER CONTROL N ADDRESS DECODER f L 4 4 1 e I OP 101 MIR A B C G I i WAlT J JXX Figure 4 23 04 Data Paths 4 73 ...

Page 107: ...AGS I 0 04 AlIJ w w I MU I r MU L t 4 3 4 3 ro e PORT A PORT 26 a CONTROL LINES f FILE 01 M V1ASTER CONTROL N ADDRESS DECODER 02 1 L t r 0 al 3 t OP 01 _L MIR A a c G n I i 01 WAlT L JXX 04 Figure 4 24 4 Data Paths Second Cycle 4 74 ...

Page 108: ...me of them serve timing and sequencing functions that are not necessary to the understanding of the CPU operation and how it affects the Data Access and Microinstruction Bus Several are described in detail in the following paragraphs and in Figure 4 25 Register Load This control line determines whether or not the output of the ALU will be gated back into the register file input port It is invoked ...

Page 109: ... l 1 DAl08 15 LOAD HIBYTE _ _D A Le e e 7 _ 1L J LOAD LOBYH REGISTER LOAD AlL1 UiO U JT P UC T L_J LOAD LIT LDM TR r i 1 LOAO TR r MODIFY LO A PORT OUTPUT OAL 8 15 L MOOtFV HI B PORT OUTPUT WAlT MASTER CONTROL 12 13 CONTROL LINES DOUBLEISINGLE DAL0B 15 DAlH lt7 Figure 4 25 Major Control Lines 4 76 ...

Page 110: ...on Modify Hi This control line is the high order analog of the previously described control line JXX This control line is invoked by the jump instruction It is made hi during the first phase four of the jump instruction if the jump instructions have been met It causes the contents of the MI register on the control chip to be placed into the LC register Load LIT This instruction controls the multip...

Page 111: ...e Trans lation Array The Programmable Translationl array serves to generate new microinstruction fetch address s as a function of several parameters These parameters are t ose which are normally considered during the decoding of macroinstruction While the Programmable Translation Array was designed speci fically to eliminate most of the overhead of macroinstruction translation it is useful for oth...

Page 112: ...the Master Control function Array No 4 and the Return Register There is also an in ut to the Location Counter from an incrementer Array No 1 Array No 1 is an 88 element array with 23 inputs There are 11 true inputs and 11 complemented inputs from the Location Counter and the RNI bit MIB17 Figure 4 27 illus trates the organization of Array No 1 Figure 4 28 illustrates the concept as opposed to impl...

Page 113: ...A 8 1 LAA n PTA 01 1 L 0 3 B r J 1071 TA L TSR r o r h__ LL T f 7 2 If TAl ARRAY ARRAY 2 3 TSR 5 r 015l M se r AESE T 14 6 01 LO NC MjB 15 M L DJA LOJB lIS JUMP I 1 0 RESET COMPUTE MASTER CONTROL 3 82 d 03 APLY BUSy 3 SyNC DIN EJ l O WAIT DOUl 5 we lACK Figure 4 26 PTA Component Interconnections 4 80 ...

Page 114: ...0 2 I 1 1 1 _ C __ _ i Ci t f t 4 J Wo 1 11 4 1M _tl11 AIt 12 13 JOii 7 ______ 0 2 ______ 0 13 ______ too u ______ 0 1 ______ Ou ______ 0 Figure 4 27 Array No 1 Organization ON I or 88 Figure 4 28 Typical Gate Array No 1 4 81 ...

Page 115: ... Array No 2 is an ORed array whose outputs are negated The array has 89 inputs 88 from Array No 1 and one from MIB17 the RNI line The seven outputs from Array No 2 represent a translation state code and become inputs into Array No 3 Figure 4M 30 illustrates the organization of Array No 2 Figure 4 31 illustrates in some detail the conceptual structure of the gate and interconnect structure of Array...

Page 116: ... l When one or more ou pu s of Arrav ol ar assp ned Array 2 will make the corresponding word available as its outputs The purpose of Arrays 01 and 02 is to provide a mapping between the present value of the Location Counter and a preselected set of translation state codes RNI INPUT 0 INPUT 1 INPUT INPUT R i INPUT 86 INPUT 81 Figure 4 31 Array No 2 Gate and Interconnect Structure 4 83 ...

Page 117: ...0 76 lB 33 4B 5A 6C 37 4F 5E 6E 79 10 35 40 5C 71 3B 57 67 73 7A IE 36 4E 63 72 7C 27 39 53 65 74 28 3A 55 66 78 The outputs of Array No 2 represent some of the inputs to Array No 3 The RNI line MIB17 deserves mention at this point It is the purpose of the RNI line to force a particular user defined state code from the mapping represented by Arrays No 1 and No 2 This state code will be independent...

Page 118: ...ue and complemented data are present Two from the translation state register Again both true and complemented data are used One input called the Q signal not generally usable It is worth noting that while there are 42 inputs in Array No 3 they are not all present at the same time The array is broken into two partitions The first partition consists of words 0 through 15 and has as its inputs the 14...

Page 119: ...ord 15 TSA TSA Q Array OUIputs Inl rupls InterrupiS OUTPUIO Output 1 Output 2 Figure 4 33 Array No 3 Interrupt Organization T msJOIlion SldlC RegIster AHilY 2 OtJ PlJt T 111 1 111011 Rf qtstl l __ __ o __ Word 17 Word 18 Word 19 A f R 0 T n A M l l o Q tl1 O iYU 6 Output 17 Output 18 Word 98 Word 99 OUIPU 97 EE3j lE 1 Figure 4 34 Array No 3 Translation Register Organization 4 86 ...

Page 120: ...n of its inputs against one of the words that make up the array If it finds a match the output associated with that word will be asserted Array No 3 is programmed with true data as eight hexadecimal digits DON T CAREs which always result in matches are created by placing both rue and complemented bits to zero Below is a data specification for the programming of Array io 3 4 87 ...

Page 121: ...ray The third control line determines whether or not the value presented to the Translation State Register will in fact be loaded into the Translation State Register Figure 4 36 illustrates the organization of this array Note that not all the outputs are complemented The two control signals LRA and LTA are true data Array No 4 will determine if any of its inputs are active If they are the word ass...

Page 122: ... selected for input to Array No 3 The oth er is to provide a four s ta te feedback as an input of Array No 3 The loading of the Trans lation State Register is controlled by an output LTSR of Array No 4 Translation Register The Translation Register holds the data presently serving as input to the Programmable Translation Array It receives its inputs from the Microinstruction Bus MIBOO MIB15 as a re...

Page 123: ...oop can be considered as the Location Counter This loop is completed wi thin one machine cycle and the main components are The Location Counter Arrays No I and No 2 which taken together perform a mapping of the Location Counter to a translation code The translation register which hOlds the macroinstruction undergoing the translation process Arrays No 3 and No 4 which take the translation code and ...

Page 124: ... not it has a match If it has a match then the appropriate output is set at the end of 02 If there is no match the translation proceeds no farther because no outputs are set At the beginning of 3 see Figure 4 39 Array No 2 samples the outputs from Array No 1 and determines whether any are active If there is a match then the translation code is generated and fed to Array No 3 also during 3 During 0...

Page 125: ...xt occurrence of jH Ig I Q Q RNO m I 01 I I MI m 1 LC II V P c B If 2 13 r LC L C m m 0 ARRAY LL ARRAY TRANSLATION CODE LRR 01 1 LRA 71 11 f TA0 10 7 1 LTA 0 3 q rU TR0 10 81 LTS R 8 0 1 Q I Q 1 01 11 I U 7 t L t TR 1 l t i 0 ARRAY ARRAV r t 3 J r sR f L r 84 12 13 i4 101 MIt SET RESET 14 6 0 t DINC MIS S MI 115 LOJA LOJB JUMP RESET J l cOMPUTe I MASTER CONTROl tJ2 _ d 3 RPl Y I 4 WAIT BUSY 3 SYNC...

Page 126: ...ODE LRR 13 LRA 11 PTA 10 LTA 0 8 a rU TR 107 1 L TSR t e l a 11 a 1 1 J 2 2 f J l b s TR ARRAY ARRAY I f 3 TSR _ l I 1015l MI SET RESET 14 6 0 LDINe MIS15 MI LOJA LOJB JUMP l l 2 RESET COMPUTE MASTE R CONTROL 3 2 and 3 RPL V I 2 BUSY 3 SyNC DIN WAIT OOUT J WB lACK Figure 4 3 8 02 Data Flow 4 93 ...

Page 127: ...11 PTA0 10 LTA 0 3 r q rU TA 1071 A L TSA r t GO 0T GO 1 2 __ Ll L 2 I _ 1l o TA ARRAY ARRAV r o 3 J f T 0 _r IJ r r r i6 Eol MI0 10 SET RESET 14 6 01 lOINe MIS 15 MI lOJA l DJG J 1 JUMP 2 AESET COMPUTE MAS fE CON TROL OJ 02 nd 03 RPLY I 2 BUSY 3 SYNC DIN g J WAIT COUT f 0 I ACI Figure 4 39 03 Data Flow 4 94 ...

Page 128: ... 10 01 LTA 0 3 G rU 10 11 A TA L TSFl 8 f 8 1 eo eo A t 2 _ Ll 2 f L 0 82 TA AARAY ARRAV r r o 8f 3 TSR 8 _r 3 c 81 r If 15 MI SET AESET 14 6 0 LOINe M18 15 MI LDJA LOJB IHt JUMP 2 RESET I COMPUTE f MASTER CONTROL 2 nd 113 8J RPLY I 2 BUSY 3 SYNC DIN r a J WAIT DOUr f we lAC Figure 4 40 4 Data Flow 4 95 ...

Page 129: ...re bits 16 and 17 are involved with control of the Location Counter Bit 16 determines whether or not the contents of the Return Register will be loaded into the Location Counter Bit 17 determines whether or not a Read Next Instruction translation will be invoked These two options are available on all instructions bits 18 through MCP1600 system as TTL levels 21 have nothing to do with control of th...

Page 130: ...Counter on the Control Chip A special case of this format is the Return From Subroutine instruction covered later CONDITIONAL JUMP FORMAT oP C I ADDRESS I 15 1211 87 0 This format provides a Jump address within a page This instruc tion is substantially the same as the Unconditional Jump format with the exception of the reduced address space It is also a two cycle instruction with the jump decision...

Page 131: ...move instruction alf as as b operation for instance in b operation for ins tance in a aft b and a can specify either a single byte data quantum or a word double byte data quantum In this latter case the designators usually point to the even addressed member of a register pair While they may both point to an odd addressed pair note carefully the instructions description for the effect If the design...

Page 132: ...clusive or Exclusive or RxRy Forms extended register Ry LSB Ax MSB Ra The register specified by the micro instruction a field Rb Designates no catagory Flag Selting The register specified by the micro instruction b field X Don t care condition 0 Flag cleared set to 0 1 Flag set Flag not affected Set accordinn to function 4 99 ...

Page 133: ...L 1 Ral Literal Ra the 8 bit constant is added to Ra Compare Literal 3 CL 1 RaJ literal The 8 bit result of the literal is compared against Ra and the annronrate flaos set And Literal 4 NL 1 I Ralll Literal_lRal The 8 bit result of a logical product of Ra and the literal are coded into Ra Test Literal 5 TL 1 IRa II Literal The 8 bit restilt of the logical product of Ra and the literal set conditio...

Page 134: ...ents of Rb 1 Rb are incremented by one and the fesult transferred 10 Rat A I_ Increment Byte by 2 94 95 ICB2 1 Rblf2 Ral The B bit contents of Rb are incremented by two and the r 5U t tram terred 0 Ra Incremen t Word by 2 96 97 ICW2 2 IRb 2 IRal The 16 bit contents of Rb l Rb are incremented by two d the result transferred to Ra l Ra Twos Complement Byte 9S 99 TCS t IRbl I Ra The S bit contents of...

Page 135: ...a and Rb are not changed Compare Word B6 B7 CW 2 RaHAbl The 16 bit difference between the contents of Ra Ra and Rb I Rb are used to set the s1atus flags at all times and the conditlcn fla s if OP Code 87 is selected Registers Ra l R a and Rb Rb are not changed Subtract Byte with Carry B8 B9 SBC 1 IRal IRb Co Aal The difference 01 the e bit contents of Rb subtracted from Aa minus the contents of C ...

Page 136: ...ded into Ra l Ra The carry flag is inserted into the high order position of Ra 1 Shift Right Byte DC DO SRB 1 IRbm J IAam The 8 bit cOntents of Rb are shifted right one bit and 10aded into Aa Shift Right Word DE OF SAW 2 IRbm I IRam The 16 bit contents 0 Rb I Rb are shifted right one bit and loaded into Ra l Ra Input Byte EWEI IB 1 1m in IDALI IRa An 8 bit byte on the OAL is loaded into the sPecif...

Page 137: ...y 2 address oeated in Rb Ra IS Cransferred to the DAL lines and a DATA READ operation is initiated The contents of Rs are incre mented by 2 Rb remains unchanged Write and Increment F5 WIB2 1 IRb Ral DAL IRa 2 Ral The t6 bit Byte by 2 address located in Rb Aa is transferred to the DAl line and a DATA WRITE operation is initiated The contents ot Aa are incremented by 2 Rb is not changed Read and Inc...

Page 138: ...ddressed unit Output Status FE OS 1 IRbiAal DAL The 16 bit contents of registers Rb Aa is transferred to the DAL lines and takes place regardless of the state of the Aeply or Busy signal DOUT is not activated and Sync is not terminated Registers Rb and Ra are unchanged No Operation FF NOP 1 This instruction causes no operation Table 4 16 Summary of Microinstruction and Status Flags ALU Status Flag...

Page 139: ...a 2 SL8 BC 8o b 1 SLW BEIBF b 2 IC8 90 91 b a 1 ICWI 92 93 b 2 ICBZ 94 95 b a 1 ICWZ 96 97 b a 2 TC8 9B 99 b a 1 TCW 9A 9B b a 2 OCB 9C 9D b a 1 0 0 0 1 OCW 9E 9F b a 2 0 0 0 1 AB A0 A 1 b a 1 AW A2 A3 b a 2 CA8 M A5 b a 1 I C CAW A6 A7 b a 2 I C ABC A8 A9 b a 1 AWC AA AB b a 2 CAD AC b a 1 CAWI AEIAF b a 2 t j e SB B0I81 b a 1 SW B2 B3 b a 2 CB B4 B5 b a 1 SW B6 B7 b a 2 SBC B8 B9 b a 1 SWC BA BB...

Page 140: ... NCW 02 03 b a 2 0 SRBC 08 09 b 1 0 0 a SRWC OA OB b 2 0 0 a SRB DC DO b 1 0 0 SRW DE OF b 2 0 0 IB EWE b 1 0 a iW E2 E3 b 2 0 a ISB E4 E5 b 0 a E6 E7 2 0 ISW x a MI EC EO b 1 LTR EE EF b 2 RIBI F0 b a WIBI Fl b 1 a RIWI F2 b 2 a WIWI F3 b 2 RIBZ F4 b 1 a WIBZ F5 b a RIWZ F6 b 2 a WIWZ F7 b 2 aa R F8 b a 1 W F9 b a 1 RA FA b a WA FB b a 1 OB FC b a 1 OW FO b a as FE b a 1 Nap FF x x 1 4 107 ...

Page 141: ...e Microinstruction Bus in a fashion to be defined below The discussion below describes the 22 different lines on the Microinstruction Bus from the standpoint of each of the various types of devices attached to it and from the standpoint of user attached devices Figure 4 41 illustrates the system inter connections iii i t 12 J 21 ROM CHIP CftlU1B i iii I i T IIlTl CONTROL DATA OALf 16 TTLI CHI CHIP...

Page 142: ...ion Bus is divided into seven partitions These partitions can carry data in both directions They assume different meanings at different points in the clock cycle of the processor set This section describes each element and its meaning as a function of the phase time in each clock cycle MIBOO MIBlO These lines serve to carry data bidirectionally between microinstruction ROMs and the Data and Contro...

Page 143: ...ycle If1struction Data from Data Chip to Control Chip MI816 Load Return Register Precharge Disable Pre hArql by MICROM MICROM by MICROM outputs at next 01 MI817 RNI Prer h HQP by MICROM M1818 M1821 TTL Outputs Valid Precl1arge by MICROM At 02 address data is transferred from the Location Counter in the Control Chip to the MICROM At 03 the address data remains valid on the bus The processor cycle i...

Page 144: ... ROM to the Data and Control Chip In the case of a micro instruction whose execution takes two cycles the second occurrence of 01 may serve to convey data from the Data Chip to the Control Chip The contents of MIBls are not significant at 02 The cycle is completed by an unconditional precharge of MIBls at 03 MIB16 This control line conveys data from the ROM to the Control and Data Chips and from t...

Page 145: ...esent four bits in the Microinstruction word and are made valid at the same time as the other outputs of the MICROM 01 The lines are unconditionally precharged Hi by the MICROM at 04 and conditionally discharged Low according to the contents of the word at 01 The user may set these outputs in any fashion he chooses They remain valid in the inclusive interval 01 to 03 Figure 4 42 illustrates their ...

Page 146: ...o r J 4 ClOCI I HAS ClOCI I HAIl CLOCr HAS CLOCI I HAlil NOt TTL OUT UTS liiliii liiii i1t A UNCONOITIONALLV OltlVEN HIGH AT A P OlfiONAllVDRIVEN LOW AT I THIS CONDITIONAL lOW WIll If VALID UNfll HE NUl IIlol Figure 4 42 TTL Output Timing CP1631B 4 113 ...

Page 147: ...y not transfer data to the Control Chip If the two cycle instruction was of the Jump class or word operation class the Data Chip will not transfer data to the Control Chip If the two cycle instruction was a LTR or IW instruction with the appropriate bits in the control field properly set then the Data Chip transfers 16 bits of data into the Control Chip This data is gated into the Translation Regi...

Page 148: ...d contents of the Location Counter MIB17 from the Microinstruction ROM controls whether or not the RNI translation will be invoked Data from the Data Chip to the Control Chip can be passed over MIBOO MIBls as a result of an LTR instruction or an IW instruction MIBls is also used by the Data Chip to send the results to the Control Chip s Master Control function informing it of the results of a cond...

Page 149: ...terfaces with all 22 lines of the Microinstruction bus It receives Microinstruction addresses on MIBOO MIBIO from the Location Counter in the Control Chip It also receives an ENABLE DISABLE signal on MIB16 from the Control Chip It sends data on MIBOO MIB17 to the Control Chip and the Data Chip MIBOO MIB15 are presented to both the Control Chip and the Data Chip These 16 bits comprise micro instruc...

Page 150: ...CHAlIIQINQ LOW ADDRESS 14I UT TRAHIIIYIONS OCCUI l ONLV ON MII_ Mi 1i LINES NIIO eH SELECT I SWItCHING TIMES AAIE MEASU UD AT AND OF SHeiflED Llvn 4 3 6 Figure 4 45 DATA ACCESS Microinstruction Bus Timing CP1631B Communications between the MCP1600 system and attached peri pheral devices or memory is conducted via a path called the Data Access Bus The Data Access Bus consists of 16 data lines DALOO...

Page 151: ... regardless of function is assigned an address and is referenced by means of this address In essence then the Data Access Bus can be conceived to consist of the following elements Data Lines DALOO DALlS Control Lines SYNC REPLY DATA OUT or DOUT DATA IN or DIN WRITE BYTE lACK BUSY Processor Control Lines 10 11 12 13 COMPUTE RESET The remainder of this section describes each of these elements of the...

Page 152: ...NC line is made high The variations on the READ instruction are primarily for address manipulation and easing the coding of I O routines They cause the address source registers to be modified in some fashion As far as the system designer is concerned the pertinent operation of this instruction class is that it causes the selected address to be placed on the Data Access lines DALOO DAL1S and the SY...

Page 153: ...EXECUTE o T F Figure 4 46 I O Instruction Condition Testing 4 120 ...

Page 154: ...F ADDRESS DALOO 15 ASSERT SYNC I I EXIT F EXIT Figure 4 47 Execution of Read Instruction 4 121 ...

Page 155: ...Register Rb is not changed 15 F4 8 b 4 a o The 16 bit address in Register Rb Ra is transferred to the M Register and a DATA READ operation is initiated The contents of Register Ra are incremented by 2 Register Rb is not changed Timing 1 cycle RIWl b READ AND INCREMENT WORD BY 1 15 F2 8 b 4 o The 16 bit address in Registers Rb Ra is transferred to the M Register and a DATA READ operation is initiat...

Page 156: ...01 Also the WRITE BYTE line is raised during the next occurrence of 01 When the addressed device is ready to transfer data it asserts the REPLY line The comments about address source register manipulation pertain to this class of instructions as they do to the READ class of instructions described above A DATA WRITE operation is distinguished from a DATA READ opera tion by the assertion of WRITE BY...

Page 157: ...T F _ EXIT Figure 4 48 ADDRESS DALOO 15 ASSERT WRITE BYTE ASSERT SYNC EXIT Execution Write Instruction 4 124 ...

Page 158: ... is transferred M Register and a DATA WRITE operation is initiated tents of Register Ra are incremented by 1 Register not changed Timing 1 cycle WIB2 b WRITE AND INCREMENT BYTE BY 2 to the The con Rb is 15 F5 8 b 4 o The 16 bit address in Registers Rb Ra is transferred to the M Register and a DATA WRITE operation is initiated The contents of Register Ra are incremented by 2 Register Rb is not chan...

Page 159: ... to the pro cessor The data present on the data access is input by the instruction to the specified register or register pair The INPUT class of instructions will not execute until a REPLY signal has been received from the device addressed by the previous READ instructions Refer to a description of the REPLY signal below for the timing required When this instruc tion is executed it sets DATA IN hi...

Page 160: ... in Register Ra Code El causes the condition flags except C to be updated The Read Data Access operation is terminated unless Bit 6 is a one which allows a Read Modify Write RMW requiring termination by an output instruction The instruction will not execute until after a Reply signal has been received from the addressed unit The optional inputs are listed below b 0 Upper Byte Bi ts 15 8 b 1 Lower ...

Page 161: ...F T INPUT LOW BYTE T INPUT HIGH BYTE I I IXIT F _ EXIT F Figure 4 49 Execution of Input Instruction 4 128 ...

Page 162: ...he instruction will not execute until after a Reply signal has been received from the addressed unit The Lower Byte is loaded before the Upper Byte The b options are listed below b 0 b 1 Load TR DAL 6 4 to GR Sets rcs b 2 Load TR DAL 8 6 to GR Sets rcs b 3 Load TR Sets rcs b 4 RMW b S Load TR DAL 6 4 to GR RMW Sets rcs b 6 Load TR DAL 8 6 to GR RMW Sets rcs b 7 Load TR RMW Sets rcs Timing 2 cycles...

Page 163: ...evices The OUTPUT instructions need the REPLY signal to be asserted before execution will proceed DATA OUT is set Hi by the processor during the first phase of the instruction to inform the peripheral device that data is presently available on the Data Access Also during this time the WRITE BYTE signal may be set to indicate the length of data on the bus The OUTPUT STATUS command operates as the O...

Page 164: ...F T F __ EXIT ASSERT WRITE BYTE PLACE DATA ON DALDO IS ASSERTDOUT I I IXIT WORD RESET WRITE BYTE Figure 4 50 Execution of Output Instruction 4 131 ...

Page 165: ...imum OW b OUTPUT WORD 15 FD 8 b 4 o The l6 bit contents of Registers Rb Ra are transferred to the M Register and the Data Lines The Data Out signal is acti vated Registers Rb and Ra are not changed Output does not take place until Reply has been received from the addressed unit Timing 1 cycle minimum OS b OUTPUT STATUS 15 FE 8 b 4 o The l6 bit contents of Registers Rb Ra are transferred to the M R...

Page 166: ...r OUTPUT Instruction respectively RA b READ ACKNOWLEDGE 15 FA 8 b 4 o The l6 bit address in Registers Rb Ra is transferred to the M Register and a DATA READ operation is initiated with the Interrupt Acknowledge line high Registers Rb and Ra are not changed The Interrupt Acknowledge signal along with one or more address bits is used to form a signal which polls I J units for the one interrupting th...

Page 167: ...n The address is valid on the bus during phases 2 3 and 4 Data is output by the processor as a result of executing an OUTPUT instruction It appears on the bus at the first 01 after the microinstruction is executed and remains on the bus for a minimum of one cycle Data is received from the Data Access into the processor by the INPUT instruction It is clocked in at 04 of the instruction cycle 4 3 6 ...

Page 168: ...ade high the second 02 of the INPUT and is a function of the READ instruction The DATA IN is made low at the end of the Input Byte or Input Word instruction or when SYNC is made low This signal can be used to control the enabling of external TTL Tri State Bus Driver Receivers Data Out TTL The DATA OUT DOUT is a Control signal from the Processor which is made high at the same time as the Write data...

Page 169: ...e normal operation as soon as BUSY is turned off 4 3 6 4 INTERRUPT RESET AND COMPUTE This section describes signals which would in the normal scheme of things be defined as processor control signals Reset RESET is a TTL level line that may be controlled by an external device Activation of the RESET line causes the Microprocessor to force 001 into the Location Counter A NOP is also forced into the ...

Page 170: ...lement his own interrupt control scheme by use of these lines and the ACKNOWLEDGE instructions 4 3 6 5 INPUT OUTPUT OPERATIONS The Data Access of the MCP1600 bec use of its flexibility can be used to configure a variety of I O schemes SeveraJ of the schemes that can be implemented were mentioned in the intro duction This section will describe the interactions of the elements that comprise the Data...

Page 171: ...for a minimum of one cycle When outputting a byte with a l6 bit data path the same byte must be placed in both the upper and the lower bytes of the port and the addressed unit takes care of storing the byte in the proper half of the word as selected by the low order address bit The time period between selection of the device by the WRITE instruction and the transfer of the data is not critical if ...

Page 172: ...I m IlU I 0 IIt l fM I Ol U I INt n JI I U 11101 rOllllwILlllllllltl Allr IV I Dl n 1 i1l Dl Hr o UlI l Ull DuIIl JI 11lC 11tlJ II Irtl ir Il I IIO IIAI Itl V IlI OIHtll ttC 16 tll M I IOJ 01 11 l lU OllClllla u l II U l lll HH M fl lie lU OJ 6 QOII c l So ant 1M Figure 4 51 Write Output Sequence f D I 1 N PUT VAL ID I N YT L w YT I NPYTHIGH B Ynl I r 01 02 03 04 01 02 03 04 01 02 03 04 01 2 03 4 ...

Page 173: ...ata is input to the processor registers by an Input Byte or Input Word instruction The Data Access operation is not terminated as in the case of a normal Read but continues for a subsequent output as specified by the Input instruction This suspended period can be used to modify the data if desired An example might be an Increment Memory instruction After modification data is transferred from the p...

Page 174: ...r the device controller requesting attention to return its device number on the subse quent INPUT instruction Figure 4 54 illustrates the operation of both the READ and WRITE Interrupt Acknowledge W I n I I I I I I 0 I I III I 01 OJ 0 1 I 01 I 0 j 0 I lit 07 I 11 r n I lUIII x 1 1U 11I f nou I V WI l lII fll I oc 1 1 1 J Il I I q II W I 11 I It I 1 I 1 1 I j 1 I 117 n1 I 1I I 11 1 1t 1 I 1M 111 11...

Page 175: ...dual circuit packages DIPS contained on the AM lOO two board set The CPU processing is handled by the set of five DIPS as described in paragraph 4 3 The control and interface modules are also described in the following paragraphs with logic and connection diagrams for each one 4 142 ...

Page 176: ...s during one of the clock phases the chip immediately tries to generate another phase I For stable operation phase 4 should not overlap phase I Each clock phase width is independently controlled by an externally applied capacitor to ground A 10 to 20 pf capacitor provides for an output clock phase width of 100 ns Logic and timing are shown in Figure 4 55 Pin Description Pin No Symbol Function 1 VB...

Page 177: ...f 1 I O LAY I DELAY I DELAY r DELAY I DELAY r v o In 01 Delay 1f2 Delay 93 Delay 4 Delay 4 1 space or Gnd VCH I I CUiC VCL OSC VOH n n VOL PHASE 1 VOH n n VOL PHASE 2 VOH n I PHASE 3 VOL VOH n VOL PHASE 4 Figure 4 55 Four phase Clock Logic and Timing 4 144 ...

Page 178: ...s or bus lines The outputs are disabled independently from the level of the clock by a high logic level at either output control input The outputs then present a high impedance and neither load nor drive the bus line Detailed operation and logic is shown in Figure 4 56 I n 1 U J 1 5 U J I 1 i3D k U I o I_ J Logic Oi gram 1111 111 I L l h I 1 1 II I uA n u Conl18etion Diagram ell t III Truth Table ...

Page 179: ... low current interface logic Logical inversion is provided with active pu11ups See Figure 4 57 for logic and connections aND II I J AII _II01_ t _ oiI r lM I If I I I I I I I I Oll I I I I I I I I rCl01 I I or r L l O 1 Figure 4 57 High Speed Hex Inverter Connections 4 146 ...

Page 180: ...output onto the high impedance state while the other input passes the data through the buffers The outputs are placed in the tri state condition by applying a high logic level to the control pins See Figure 4 S8 for logic diagram and truth table Logic and Connection Diagram Truth Table 1 15 U II INl U1I OOT UT Ii V H X Hj l L H H L L L 11 VI AJ VI Al 1 1 110 Figure 4 58 Tri State Buffer Connection...

Page 181: ... state while the other input passes the data through the buffer The outputs are placed in the tri state condition by applying a high logic level to the control pins See Figure 4 59 for logic diagram and truth table Logic and Connection Diagram 1I 12 nAliYli U I _ 11 11 14 11 U 11 II I Al 1 1 A2 n 1 1 2 0 Truth Table INfltJTS OUTPUT jj y H X Hi Z L H L L L H Figure 4 59 Hex Tri State Buffer Connect...

Page 182: ...tal expansion without the need for external circuitry Data inputs and outputs are active at the low logic level See Figure 4 60 for logic diagram and truth table nOp VIew AO nOlo 1 I a fUNCTION tABLE INPUTS OUTil UTS AO G 0 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H Figure 4 60 Eight Line to Three Line Encoder Connections 4 149...

Page 183: ... one of the two sources and route it to the four outputs as true data no inversion See Figure 4 61 for logic diagram and connections T O Jl 011 cc Mull or I If g ICt I c D IS o A l l ul POSJflve L OGIC LOw tOQ c 1 l S II I U A inCluU High logic I S eeu e n II Figure 4 61 Data Selector Multiplexer Connections 4 150 ...

Page 184: ... signals and provides high current and high voltage output levels suitable for driving MOS circuits Specifically it can be used to drive address control and timing inputs for several types of MOS RAMS See Figure 4 62 for logic and connections DUAL1N LINE PACKAGIE lTO VIEWI Veel 2Y vee schematic each driver 1 4 1 Figure 4 62 NAND TTL TO MOS Driver Connections 4 151 ...

Page 185: ...RESET AND CLEAR Board 2 U6 UIS U19 U23 U31 U32 U34 U36 See Figure 4 63 for logic diagram and truth table TRUTH TABl E INPUTS OUTPUTS PO C R CLK D D ii H X X H H L X X H x x W H H H H H L H H f L H H H X DO 00 Figure 4 63 D Flip Flop Connections 4 152 ...

Page 186: ... U40 USO US1 See Figure 4 69 for logic diagram and truth table Connection Diagram t l U t i i rJ r 1 r J Jr l J t t Truth Table TRUTH T at E PUTS OUTPUTS PR eLK J K Q a L x X X H H I L no 00 H I H L H H H L H H H H TOGGLE H H X X 00 00 Figure 4 64 J K Flip Flop Connections 4 153 ...

Page 187: ...I put J ol 6lo lllV 1 pulse To U II the lOla nal timing resiuor of 54121 74121 connllCt AINT 10 Vee An Kurnalliming capacitor may b connected between CeXT nd F teXr CeXT politivel Fo accurate repeatable puIs widlhJ connect an lIJOlternal Ii ot b lw tn ReXr CeXT t ld Vee with RINT open eircuitlld To ohillin variahle pulse wlnlh COnnect 8llternal variablll islal1u btlween R I lr or REXr CEXT Bf d Ve...

Page 188: ...e internal oscillator runs continuously even while the output is disabled A pulse synchronizer ensures that the first output pUlse is neither clipped nor extended Duty cycle of the output pulses is fixed a approximately 50 percent See Figure 4 66 for logic diagram and connections The highly stable oscillator can be set to operate at any frequency between 0 12 Hz and 50 MHz typically The output fre...

Page 189: ...gic diagram and truth table Connection and Logic Diagram Truth Table INPUTS OUTPUTS ENAILE SELlct Gl C A VO VI V2 V3 V V V 7 X H X 1 x H H H H H H H H L X X X X H H H H H H H H H L L L L L H H H H H H H H L L H H L H H H H H H H L H H H L H H H H H H L L H H H H H L H H H H H L H L H H H H L H H H H L H L H H H H H H L H H H L H H L H H H H H H L H H L H H H H H H H H H H L VI vj Yf SUH I P J G2 G...

Page 190: ...he transition time of the positive going pulse When the clock input is at either the high or low level the D input signal has no effect at the output See Figure 4 68 for logic diagram and truth table Logic Diagram Connection Diagram t H H 1 ClhA CIOCO 11 IJI I If I IJt til QS Ql UDC I 1 11 II 11 n Truth Table I OUTPUTS el iA CLOCK 0 0 0 l X X l H H I H H l H I l l H H l X a a H High Lewlllt awl L ...

Page 191: ...trol line to gate the output into a high impedance state while the other passes the data through the buffer The outputs are placed in the tri state condition by applying a high logic level to the control pins See Figure 4 69 for logic diagram and truth table Logic Diagram Truth Table tiIJ lU aU t z Figure 4 69 Tri State Octal Buffer Connections 4 158 ...

Page 192: ... ...

Page 193: ...irements of Sections Two and Three of this manual are met Should a problem arise after the circuit card has been in operation perform the following preliminary checks to identify and locate the fault 1 Check all cabling for proper seating of connectors 2 Check the circuit board for proper seating in the slot 3 Check all power connections for correct voltages 4 Check all jumper options to ensure co...

Page 194: ...y issued by Alpha Microsystems Irvine California Complete details of the warranty are included with the circuit board Should a problem arise with this circuit board call your dealer or the Alpha Micro International Support Services Administrator for information 5 2 ...

Page 195: ...SECTION 6 SCHEMATIC AND PARTS LIST 6 1 ...

Page 196: ......

Page 197: ...1S SH 2 4 5 MIBts SH 2 5 I r I r MIB 7 SH 2 5 U7 MIB21 SH 21 13 12 Bl93 U31 U32 CP1631 29 CP1631 30 MICROH MICROM U7 MIBI9 SH 2 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I 9 3 MIB2Q SH 21 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I II BIS3 MIBl8 ISH 2 l l HH l l l l l l tttttt t j j j HHHH l 4 C 8 c CPU st l IJI 133M SH 1 134M S...

Page 198: ...51 sI7 l oI J21 814151S lzh DALIS ISH S o I c CP1Gl1 8 OATR CHIP I4AIT SH 5 I 8 I Be 17flf R7S ln E SCHEMATIC AM IOO CPU NO 1 IIR I SYSTEMS IRVTNE CA 92714 0l Il 27 ZS zs z za 15 4 33 32 301 9 mtr 81M SH 1l 82M SH 1l 13M SH 1l J 84H SH 11 MI800 ISH 2 3J MIeOI H 2 3 HlB02 H Z 3l I M1803 ISH 2 3 g l 111806 fSH 2 3 I MISDl SH 2 3 r 11808 SH 2 9 HIBD9 ISH 2 3 I ilB10 ISH 2 3 I11Bll ISH 2 3 HfB12 tSH 2...

Page 199: ...4M SH 1 20 1 MIBOO SH 2 3J 3S HIBDl SH 2 3 MIB02 SH 2 3 36 MIaoa SH 2 a 35 1804 SH 2 3 M IS05 SH 2 3 MIB06 SH 2 3 KIS07 SH 2 31 A MI808 SH 2 3 HIB09 SH 2 3 29 HIBIO SH 2 3 28 MISII ISH 2 3 27 MISl2 SH 2 3 MIBta SH 2 a 111814 ISH 2 3 MIBI5 SH 2 3 MIBtS SH 2 3 ll PAR J2 HI817 SH 2 3 __ 7 BUSY 14 8 RPL1 IS 12 RST 15 10 RTCFF 12 5 I2FF SH 7 i HALTIID I 1 c B A CPU rl L P jl A SYSTEMS IRVINE CA 92714 B...

Page 200: ...I 4 7K 027 014 91 12 11 DALH SH 4 8 1 7 R20 LS 7 5V U27 1 1 n J IS 92 14 DALI3 ISH 4 7 1 11 551 1 2 Is R20 Lsa7 14 h CLRM N 3 SV u27 BDAlI SH 8J t t t Ol Ql DALoa SH 4 7 8 4 7K lSr 15 BOALiO SH 8 13 02 U9 Q2 4 DRL 02 SH 4 7 8 DIS 93 1 I L S 7o ORL14 SH 4 8 aDAl09 SH 8J 12 03 03 5 DALOI SH 4 7 8 RIg 5V SOAlOS SH BJ t 04 8551 Q4 6 DALOO SH 4 7 8 4 7K _ U27 61 017 43 181 17 DAL15 CSH 4 9 f l2 62 l I ...

Page 201: ... OAL02 SH 4 6 8 SV 4 7K US US l 2 3 L c 2 J9 J _l R2 8097 BILS9 DAL03 SH 4 S 8 3 sv 4 7K us us Qj or 9 4 3 R8 I 8097 8 LS97 I 0AL04 SH 4 6 8 A_ 5V t I2FF SH SJ 4 7K US us t 29 11 l r_lJ 5 f SU __ RS 8097 c 8 LS97 OALOS ISH 4 6 8 _ 5V 15 4 L ar 9 8 I L S S 7 0AL06 SH 4 6 8 T R US EARS l l 2l 1 1 12FF 11 I SJ lc LS cS c7 OAL07 ISH 4 6 8 I lis EXT ADDRESS lL PH A REGISTER SELECT STATUS BHE llrCllllSY...

Page 202: ...12 lSH 4 6 t8 2 A1 S 6 4 10 U26 8tLSS7 17 n 9 101 81LS97 3 81 Ut8 8097 38 Ull 5 02 Y2 7 16 15 OAL14 SH 4 6 14 U19 82 W 026 BILS97 13 3 BILS9 11 A3 Y3 B097 40 I U11 U19 83 lB 17 14 Rot flL U26 I8i LSS7 CRUS ISH 4 6 12 H 14 11 13 84 13 90 101 81LS97 l 9DAl12 ISH 6 9 74157 I 0097 llI U11 U19 BOAL14 SH 5 9 13 DRUS SH 4 6 tS BOALlS SH 6 9 12 026 81LS974 15 11 Iol 19 81LS97 BCAUS SH S 9 B097 19 t t5 BDA...

Page 203: ...IA lJ22 7 I RR03 ISH 10 3097 31 lAS lJ22 t RA02 SH 10 12 11 3097 81 1A2 lJ22 L RA01 ISH 101 I B l97 i 80 IA1 9PUt 2 CLKCLR I l BCAlOS SH 8 3 01 01 BDAL04 ISH 8 4 D2 Q2 5 I BDALOg ISH 8 6 D3 U14 Q3 7 SDALoe SH 81 11 04 Q4 _0 BORLOI H 8 13 Q 12 BOAlOO ISH 8 14 os QS 4LS17 hT CLKCLR BDAUt ISH 8 3 D1 01 2 U13 BOALoe SH 8 11 04 Q4 10 BOALO tsH at 13 05 Q5 1 2 J BCALOS SH 8 14 06 QS 15 I 4LS17 B c lAO S...

Page 204: ... a7 Al0 RAl1 iSH 91 141 5 B097 U29 5 97 All J 8097 1 15 U24 S 6 7 RA04 tSH 9 Rt 1 1 4 sa A12 RA12 SH 9 a Bl B097 RA05 SH 9l A2 27 U24 I fo RAta ISH 9 SB2 U1S 4 5 BS RIa lIAS Y3I o RAOS SH 9 8097 RA14 ISH 9 10 S3 flo4 RA07 lSH 9 14 Y4 12 la 2 a B6 A14 RAtS SH 9 B097 74157 l IJ24 I n 9 B097 A15 1 XO_RANTL XDHR6RANT SH 9 ADDRESS OUT 1 I XLPHA SySTEMS IRVINE CA 92714 aa17 SCHEMATIC AM IOO CPU NO 1 ldi...

Page 205: ...74LSOO 74LSto 74CIDa 74LSQD 11 I DBIN SH 8 12 U25 3 JFOUR SH 8 DIN SH 6 E JFOUR SH B 74LS02 1 1 PR 9 FIVE rSH 7 m 13 J Q 10 elK OOUI SH 3 11 U16 8 12 K li l MSYNCI ISH B 10 U21 B S O I usa 74LSOO 74m iS JFIVE r H 8 JSEVEN SH 8 74LSOO 3 JREST rSH Sl 2 PR lIU49 3 3 J Q I 1 5 elK READY SH 8 1U27 4 2 K liS SIX SH SJ 74LS02 751 3 10 ll PR SEVEN rSH 71 13 J Q U3 elK HIBYTE SH 8 1 12 5 S 12 K li l JBFF S...

Page 206: ... I j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j ...

Page 207: ...FFER OCTAL IC HEX INVERTER IC HEX D FLIPFLOP IC 8 INPUT NAND GATE IC QUAD 2 TO 1 DATA SELECTOR IC DATA CHIP WD1600 IC CONTROL CHIP WD1600 HEADER IC 16 PIN RESISTOR PACK SIP 4 7K IC MICROM 1 WD1600 IC MICROM 2 WD1600 IC MICROM 3 WD1600 SCREW 6 32 X 250 NUT HEX 6 32 STL SM PATTERN WASHER LOCK 6 32 DWF OOIOI OO CNF OOOOI OO CNS 00040 00 CNS 00020 00 CNS 00016 00 CNS 00014 00 CNS 00008 00 HDM OOOOO OO...

Page 208: ...4 01 l ICl 74138 01 PCB CPU 2 AM lOO 1 CONN FLAT CABLE 40 PIN 1 SOCKET 16 PIN DIP 15 SOCKET 14 PIN DIP 34 HEATSINK 1 000WI 500 HT 710LG 2 IC REGULATOR 5V 2 CRYSTAL 4 MHZ 1 HEADER OPTION AM IOO 1 CAPACITOR 15 UF 20V 4 CAPACITOR 01 UF 18 CAPACITOR 10 PF 4 CAPACITOR 47 UF 1 CAPACITOR 68 PF 1 CAPACITOR 150 PF 1 RESISTOR 47 K 1 4W 5 CAR 1 RESISTOR 5 6 K 1 4W 5 CAR 1 RESISTOR PACK SIP 4 7K 2 RESISTOR 15...

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