ZYNQ Ultr FPGA Board AXU2CGA/B User Manual
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Part 13: 40-Pin Expansion Header
The AXU2CGA/B board is reserved with two 0.1-inch standard pitch 40-pin
expansion ports J12 and J15, which are used to connect the ALINX modules or
the external circuit designed by the user. The expansion port has 40 signals, of
which 1-channel 5V power supply, 2-channel 3.3 V power supply, 3-channle
ground and 34 IOs.
Do not directly connect the IO directly to the 5V device
to avoid burning the FPGA. If you want to connect 5V equipment, you
need to connect level conversion chip.
The IO port of the J15 expansion port is connected to the ZYNQ chip
BANK25 and BANK26, and the level standard is 3.3V. The schematic diagram
of the design is shown in Figure 13-1:
Figure 13-1: Expansion Header Schematic
J12 Expansion Header ZYNQ Pin Assignment
J12 Pin
Signal Name
Pin Number
J12 Pin
Signal Name
Pin Number
1
GND
-
2
VCC5V
-
3
IO1_1N
F7
4
IO1_1P
G8
5
IO1_2N
F6
6
IO1_2P
G6
