ZYNQ Ultr FPGA Board AXU2CGA/B User Manual
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Figure 7-1: DP interface design Schematic
The DisplayPort interface ZYNQ pin assignment is as follows:
Signal Name
ZYNQ Pin Number
ZYNQ
Pin
Number
Description
GT0_DP_TX_P
PS_MGTTXP3_505
B23
Low bits of DP Data
Transmit Positive
GT0_DP_TX_N
PS_MGTTXN3_505
B24
Low bits of DP Data
Transmit Negative
GT1_DP_TX_P
PS_MGTTXP2_505
C25
High bits of DP Data
Transmit Positive
GT1_DP_TX_N
PS_MGTTXN2_505
C26
High bits of DP Data
Transmit Negative
505_DP_CLKP
PS_MGTREFCLK2P_50
5
C21
DP Reference Clock
Positive
505_DP_CLKP
PS_MGTREFCLK2N_50
5
C22
DP Reference Clock
Negative
DP_AUX_OUT
PS_MIO27
J15
DP Auxiliary Data Output
DP_AUX_IN
PS_MIO30
F16
DP Auxiliary Data Input
DP_OE
PS_MIO29
G16
DP Auxiliary Data Output Enable
DP_HPD
PS_MIO28
K15
DP Insertion Signal Detection
