FPGA Development Board AX301 User Manual
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Figure 3-1: The FPGA chip on the Board
Part 3.1: JTAG Interface
First of all, let's talk about the configuration and debugging interface of
FPGA: JTAG interface. The function of the JTAG interface is to download the
compiled program (.sof) into the FPGA or the FLASH configuration program
(.jic) to the SPI FLASH. After the sof file is downloaded to the FPGA, it will be
lost after power failure. You need to power on and download again. At this time,
we can convert the sof file into a jic file through the Quartus software. After
downloading the jic file to the development board's FLASH through JTAG, it will
not be lost after power off, and the FPGA will read the jic configuration file in
FLASH and run after power on again.
Figure 3-2 is the schematic part of the JTAG port, which involves the four
signals TCK, TDO, TMS, TDI. These four signals are directly derived from the
FPGA pins, and each signal has a diode overvoltage protection circuit on the
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