Alinx AX301 User Manual Download Page 7 | Manualshive

Page: 7 / 36

Alinx AX301 User Manual Download Page 7

FPGA Development Board AX301 User Manual

7 / 36

Amazon Store: https://www.amazon.com/alinx

such as 4.3-inch TFT module and AD / DA module



The JTAG port is reserved for debugging and program curing of the

FPGA.



1 Micro SD card slot, support SPI mode One 6-digit digital tube, can

display 6 digits dynamically

Part 2: Power Supply

The AX301 development board is powered by USB. Use a MINI USB

cable to connect the development board to the computer's USB and press the
power switch to power the development board. The power supply design
diagram of the development board is as Figure 2-1:

Figure 2-1: Power Supply Schematic

The development board is powered by USB and generates three power

sources: + 3.3V, + 2.5V, and + 1.2V through three LDO power chips to meet the
bank voltage and core voltage of the FPGA.

In the PCB design, a 4-layer PCB is used, and a separate power supply

layer and GND layer are reserved, so that the power supply of the entire
development board has very good stability. Test points for each power supply
are reserved on the PCB so that the user can confirm the voltage on the board.

Amazon

Store:

https://www.amazon.com/alinx

Contact

Email:

[email protected]

«
...
5
6
7
8
9
...
»

Summary of Contents for AX301

Page 1: ...FPGA Development Board AX301 User Manual A m a z o n S t o r e h t t p s w w w a m a z o n c o m a l i n x C o n t a c t E m a i l r a c h e l z h o u a l i n x c o m...

Page 2: ...tore https www amazon com alinx Version Record Revision Date Release By Description Rev 1 0 2020 01 01 Rachel Zhou First Release A m a z o n S t o r e h t t p s w w w a m a z o n c o m a l i n x C o n...

Page 3: ...art 4 50M Active Crystal 12 Part 5 SPI Flash 13 Part 6 SDRAM 14 Part 7 EEPROM 24LC04 17 Part 8 Real time clock DS1302 18 Part 9 USB to Serial Port 19 Part 10 VGA Interface 21 Part 11 SD Card Slot 24 P...

Page 4: ...are two ALINX standard 40 pin 2 54 pitch expansion ports a total of 34 2 68 IOs In addition 5V power 3 3V power and multiple GNDs are also available It is a very good choice for DIY players In additio...

Page 5: ...own below The main parameters as below Parameters Value Logic elements LEs 6272 Embedded memory Kbits 270 Embedded 18x18multipliers 15 Global Phase Locked Loop PLLs 2 Global Clock Networks 10 Maximum...

Page 6: ...lay 65536 colors can display color pictures and other information One piece of RTC real time clock equipped with a battery holder the battery model is CR1220 One EEPROM 24LC04 with IIC interface 4 red...

Page 7: ...power supply design diagram of the development board is as Figure 2 1 Figure 2 1 Power Supply Schematic The development board is powered by USB and generates three power sources 3 3V 2 5V and 1 2V th...

Page 8: ...GA packages such as 144 pin 208 pin FPGA chips Their pin definitions are composed of numbers such as 1 to 144 1 to 208 and so on When we use a BGA packaged chip the pin names become letters numbers su...

Page 9: ...need to power on and download again At this time we can convert the sof file into a jic file through the Quartus software After downloading the jic file to the development board s FLASH through JTAG...

Page 10: ...TAG port on the FPGA Board Part 3 2 FPGA power and GND pins Next let s talk about the power pins of the FPGA It includes the power supply pin core voltage pin analog voltage and phase locked loop powe...

Page 11: ...GA analog power supply pin which is connected to 2 5V VCCD_PLL is the FPGA phase locked loop power supply pin and also connected to 1 2V The power connection diagram of the FPGA chip is shown in Figur...

Page 12: ...nnected to FPGA global input clock pin CLK1 pin E1 This CLK1 can be used to drive the user logic circuit in the FPGA The user can configure the FPGA s internal PLL Phase Locked Loop to divide and mult...

Page 13: ...cteristics in use SPI FLASH can be used as the boot image of the FPGA system These images mainly include the JIC configuration files for the FPGA soft application code and other user data files The sp...

Page 14: ...s an SDRAM chip on board model HY57V2562GTR capacity 256Mbit 16M 16bit 16bit bus SDRAM can be used for data buffering For example the data collected by the camera is temporarily stored in SDRAM and th...

Page 15: ...ual 15 36 Amazon Store https www amazon com alinx Figure 6 1 SDRAM schematic Figure 6 2 SDRAM on the FPGA Board A m a z o n S t o r e h t t p s w w w a m a z o n c o m a l i n x C o n t a c t E m a i...

Page 16: ...J14 S_DQM 1 G15 S_BA 0 G11 S_BA 1 F13 S_A 0 F11 S_A 1 E11 S_A 2 D14 S_A 3 C14 S_A 4 A14 S_A 5 A15 S_A 6 B16 S_A 7 C15 S_A 8 C16 S_A 9 D15 S_A 10 F14 S_A 11 D16 S_A 12 F15 S_DB 0 P14 S_DB 1 M12 S_DB 2...

Page 17: ...nicates via the IIC bus The EEPROM is generally used in the design of instruments and meters and is used to store some parameters This kind of chip is easy to operate and has a very high price perform...

Page 18: ...accurate clock source to the clock chip so that the RTC can accurately provide clock information to the product At the same time in order to power off the product the real time clock can still operat...

Page 19: ...e 8 1 DS1302 schematic Figure 8 12 DS1302 on the FPGA Board DS1302 interface pin assignment Pin Name FPGA Pin RTC_SClK P6 RTC_nRST N8 RTC_DATA M8 Part 9 USB to Serial Port The development board contai...

Page 20: ...ement the USB to serial port function You can use a USB cable to connect it to the USB port of the PC for serial data communication The schematic diagram of the serial port is shown in Figure 9 1 Figu...

Page 21: ...een in use ever since The VGA interface is also called the D Sub interface The VGA interface is a D type interface with a total of 15 pinholes divided into three rows of five What is more important ar...

Page 22: ...output digital signals and R G and B required by VGA are analog signals The digital to analog signals of VGA are implemented by a simple resistor circuit This resistor circuit can generate 32 gradien...

Page 23: ...x Figure 10 2 VGA Interface Schematic Figure 10 3 VGA Interface on the FPGA Board VGA interface pin assignment Pin Name FPGA Pin Description VGA_D 0 C3 BLUE 0 A m a z o n S t o r e h t t p s w w w a m...

Page 24: ...n Participants Toshiba and SanDisk Corporation in the United States carried out substantial research and development to complete it In 2000 these companies initiated the establishment of the SD Associ...

Page 25: ...1 1 SD card slot schematic Figure 11 2 SD card slot on the FPGA Board SD card slot pin assignment SD Mode Pin Name FPGA Pin SD_NCS D11 SD_DIN F10 SD_CLK D12 SD_DOUT E15 A m a z o n S t o r e h t t p s...

Page 26: ...r LEDs is shown in Figure 12 1 When the FPGA pin output is logic 0 the LEDs will off When the output is logic 1 the LED is lit Figure 12 1 User LEDs Schematic Figure 12 2 User LEDs on the FPGA Board L...

Page 27: ...low level 0 release to high level 1 The schematic diagram of the four keys is shown in Figure 13 1 Figure 13 1 4 user keys schematic Figure 13 2 4 users keys on the FPGA Board Keys Pin assignment Key...

Page 28: ...lay can be connected to the display through a TFT LCD screen or a VGA interface Regarding the camera selection users can choose according to their actual needs The CMOS camera interface schematic is s...

Page 29: ...4 PIN 15 N5 CMOS_D5 PIN 16 M6 CMOS_D1 PIN 17 N6 CMOS_RESET PIN 18 M7 CMOS_PWDN Part 15 Digital Tube Nixie tube is a very common display device generally divided into seven segment digital tube and eig...

Page 30: ...long as the scanning speed is fast enough the impression is a group Stable display data without flickering The same sections of the six in one digital tube are connected together with a total of 8 pi...

Page 31: ...6 Amazon Store https www amazon com alinx Figure 15 2 Digital tube schematic Figure 15 3 Digital tube on the FPGA Board A m a z o n S t o r e h t t p s w w w a m a z o n c o m a l i n x C o n t a c t...

Page 32: ...EL 2 M10 The third digital tube on the right SEL 3 N11 The fourth digital tube on the right SEL 4 P11 The fifth digital tube on the right SEL 5 M11 The sixth digital tube on the right Part 16 Buzzer T...

Page 33: ...V power supply 3 channle ground and 34 IOs These IO ports are independent IO ports and are not multiplexed with other devices The IO port is connected to the FPGA pin and the level is 3 3V Do not dir...

Page 34: ...tic Figure 17 2 Expansion header J2 schematic Figure 17 3 is the J1 and J2 expansion ports on the FPGA Development Board Pin1 Pin2 and Pin39 Pin40 of the expansion ports have been marked on the board...

Page 35: ...ment Pin Number FPGA Pin Pin Number FPGA Pin 1 GND 2 VCC5V 3 T14 4 R13 5 T13 6 R12 7 T12 8 R11 9 T11 10 R10 11 T10 12 R9 13 T9 14 R8 15 T8 16 R7 17 T7 18 R6 19 T6 20 R5 21 T5 22 R4 23 T4 24 R3 25 T3 2...

Page 36: ...Pin Pin Number FPGA Pin 1 GND 2 VCC5V 3 B1 4 C2 5 B3 6 A2 7 B4 8 A3 9 B5 10 A4 11 B6 12 A5 13 B7 14 A6 15 B8 16 A7 17 B9 18 A8 19 B10 20 A9 21 B11 22 A10 23 B12 24 A11 25 B13 26 A12 27 D5 28 A13 29 C...

Reviews:

No comments