Alinco DR-235T, User Manual

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CIRCUIT DESCRIPTION ޓ ޓ DR-235
1) Receiver System
The receiver system is a double superheterodyne system with a 30.85 MHz first IF and a 455 kHz second
IF.
1. Front End
The received signal at any frequency in the 216.000MHz to 279.995MHz range is passed through the low-
pass filter (L116, L115, L114, L113, C204, C203, C202, C216 and C215) and tuning circuit (L105, L104
and D105, D104), and amplified by the RF amplifier (Q107). The signal from Q107 is then passed through
the tuning circuit (L103, L107, L102, and varicaps D103, D107 and D102) and converted into 30.85 MHz
by the mixer (Q106). The tuning circuit, which consists of L105, L104, varicaps D105 and D104, L103,
L107, L102, varicaps D103, D107 and D102, is controlled by the tracking voltage form the VCO. The
local signal from the VCO is passed through the buffer (Q112), and supplied to the source of the mixer
(Q106). The radio uses the lower side of the superheterodyne system.
2. IF Circuit
The mixer mixes the received signal with the local signal to obtain the sum of and difference between them.
The crystal filter (XF102, XF101) selects 30.85 MHz frequency from the results and eliminates the signals
of the unwanted frequencies. The first IF amplifier (Q105) then amplifies the signal of the selected
frequency.
3. Demodulator Circuit
After the signal is amplified by the first IF amplifier (Q105), it is input to pin 24 of the demodulator IC
(IC108). The second local signal of 30.395 MHz , which is oscillated by the internal oscillation circuit in
IC108 and crystal (X104), is input through pin 1 of IC108. Then, these two signals are mixed by the
internal mixer in IC108 and the result is converted into the second IF signal with a frequency of 455 kHz.
The second IF signal is output from pin 3 of IC108 to the ceramic filter (FL101 or FL102), where the
unwanted frequency band of that signal is eliminated, and the resulting signal is sent back to the IC108
through pins 5.
The second IF signal input via pin 5 is demodulated by the internal limiter amplifier and quadrature
detection circuit in IC108, and output as an audio signal through pin 12.
4. Audio Circuit
The audio signal from pin 12 of IC108 is amplified by the audio amplifier (IC104:A),and switched by the
signal switch IC (IC111) and then input it to the de-emphasis circuit.
and is compensated to the audio frequency characteristics in the de-emphasis circuit (R203, R207, R213,
R209, C191, C218, C217) and amplified by the AF amplifier (IC104:D). The signal is then input to volume
(VR1) . The adjusted signal is sent to the audio power amplifier (IC117) through pin 1 to drive the speaker.
5. Squelch Circuit
The detected output which is outputted from the pin 12 of IC108 is inputted to pin 19 of IC108 after it was
been amplified by IC104:A and it is outputted from pin 20 after the noise component was been eliminated
from the composed band pass filter in the built in amplifier of the IC, then the signal is rectified by D106
to convert into DC component. The adjusted voltage level at VR101 is delivered to the comparator of the
CPU.
The voltage is led to pin 2 of CPU and compared with the setting voltage. The squelch will open if the
input voltage is lower than the setting voltage.
During open squelch, pin 30 (SQC) of the CPU becomes "L" level, AF control signal is being controlled