Alinco DR-135, Service Manual

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9) PLL Synthesizer Circuit (DR-435)
1. PLL
The dividing ratio is obtained by sending data from the CPU (IC1) to pin 2 and
sending clock pulses to pin 3 of the PLL IC (IC501). The oscillated signal from
the VCO is amplified by the buffer (Q503 and Q501) and input to pin 15 of
IC501. Each programmable divider in IC501 divides the frequency of the input
signal by N according to the frequency data, to generate a comparison frequency of
5 or 6.25 kHz.
2. Reference Frequency Circuit
The reference frequency appropriate for the channel steps is obtained by dividing
the 21.25 MHz reference oscillation (X103) by 4250 or 3400, according to the
data from the CPU (IC1). When the resulting frequency is 5 kHz, channel steps
of 5, 8.33, 10, 15, 20, 25, 30, and 50 kHz are used. When it is 6.25 kHz, the 12.5
kHz channel step is used.
3. Phase Comparator Circuit
The PLL (IC501) uses the reference frequency, 5 or 6.25kHz. The phase
comparator in the IC501 compares the phase of the frequency from the VCO
with that of the comparison frequency, 5 or 6.25kHz, which is obtained by the
internal divider in IC501.
4. PLL Loop Filter Circuit
If a phase difference is found in the phase comparison between the reference
frequency and VCO output frequency, the charge pump output (pin 13) of IC501
generates a pulse signal, which is converted to DC voltage by the PLL loop
filter and input to the varicap of the VCO unit for oscillation frequency control.
5. VCO Circuit
A Colpitts oscillation circuit driven by Q502 directly oscillates the desired frequency.
The frequency control voltage determined in the CPU (IC1) and PLL circuit is
input to the varicaps (D502 and D503). This change the oscillation frequency,
which is amplified by the VCO buffer (Q503,504) and output from the VCO unit.
10) CPU and Peripheral Circuits (DR-135 DR-235 DR-435)
1. LCD Display Circuit
The CPU turns ON the LCD via segment and common terminals with 1/4 the
duty and 1/3 the bias, at the frame frequency is 64Hz.