4. System Architecture and Reference
Design
4
4
.
.
1
1
A
A
U
U
9
9
5
5
2
2
5
5
B
B
l
l
o
o
c
c
k
k
D
D
i
i
a
a
g
g
r
r
a
a
m
m
Figure 4.1 AU9525 Block Diagram
XCVR
Processor
EEPROM
Interface
ROM
Smart
Card FIFO
Reset
3.3V
Voltage
Regulator
USB
Upstream
Port
Card Eject
Card Reset
Card Insert
Optional
256 Bytes
EEPROM
Card Data
Card Clock
Smart
Card
Control
RAM
USB
FIFO
USB
SIE
12MHz
XTAL
3.3
Card
Power
AU9525 USB Smart Card Reader Controller V1.00W
6
